Epson S1C31D50 Technical Manual

Technical Manual for Epson S1C31D50 Microcontrollers, Motherboard (425 pages)

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1865/1865123-s1c31d50.pdf file (16 Sep 2023)
  • Manufacturer: Epson
  • Category of Device: Microcontrollers, Motherboard
  • Document: S1C31D50, File Type: PDF Technical Manual
  • Updated: 16-09-2023
  • Count of Pages: 425
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Epson S1C31D50 Microcontrollers, Motherboard PDF Technical Manual (Updated: Saturday 16th of September 2023 04:19:13 AM)

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Compatible devices: S1C33L26, S5U13C00P00CX00, S5U13A04B00C, S5U1C17611T2, S5U13L03P00C100, S5U13A05P00C100, S1R72U06, S5U13517P00C100.

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Text Version of Epson S1C31D50 Technical Manual (Summary of Contents)

(Ocr-Read of the Epson S1C31D50 Document (Main Content), UPD: 16 September 2023)
  • 337, Epson S1C31D50 21 HW Processor (HWP) and Sound Output S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 21-25 (Rev. 2.00) Error Status Register Register name Bit Bit name Initial Reset R/W Remarks ERROR 15–0 ERROR[15:0] 0x0000 H0 R – Bits 15–0 ERROR[15:0] These bits indicate the error that has occurred while the …

  • 258, Epson S1C31D50 17 16-BIT PWM TIMERS (T16B) 17-12 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) 0xffff 0x0000 RUN = 1 Data (W) → CC[15:0] Data (W) → CC[15:0] MODEN = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 Data (W) → MC[15:0]…

  • 10, CONTENTS viii Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) 15.5.1 Register Access Mode ........................................................................................ 15-9 15.5.2 Memory Mapped Access Mode .....................................................................…

  • 340, Epson S1C31D50 21 HW Processor (HWP) and Sound Output 21-28 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) SDAC Mode Register Register name Bit Bit name Initial Reset R/W Remarks SDACMOD 15–9 – 0x00 – R – 8 PWMOUTEN 0 H0 R/W 7–1 – 0x00 H0 R 0 MODE 0 H0 R/W Bits 15–9 Reserved Bit 8…

  • 424, REVISION HISTORY Revision History Code No. Page Contents 413699401 All New establishment 413699403 All Appended “D51” to the model names (S1C31D50/D51) P1-1, 1-3, 4-1, 21-1 to 6, 21-18, 23-2 Added descriptions of the S1C31D51, and modified the figures/tables Differences between S1C31D50 and S1C31D51 …

  • 321, 21 HW Processor (HWP) and Sound Output S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 21-9 (Rev. 2.00) Note: The volume level can be adjusted by rewriting the VOLUME_n.VOLUME[15:0] bits even while playback is in progress. The playback speed cannot be changed while playback is in progress. …

  • 221, Epson S1C31D50 15 Quad Synchronous Serial Interface (QSPI) 15-36 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Table 15.8.5 Settings of Data Line Drive Length during Dummy Cycle QSPI_nMMACFG2.DUMDL[3:0] bits Data line drive length 0xf 16 clocks 0xe 15 clocks 0xd 14 clocks 0xc 13 clocks 0xb …

  • 355, Epson S1C31D50 22 ELECTRICAL CHARACTERISTICS 22-14 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) SDA n SCLn S t f t BUF tHD:STA 1/fSCL 1st clock cycle tf 9th clock cycle S: START condition Sr: Repeated START condition P: STOP condition tr tHD:DAT tHIGH tSU:STA tLOW tr tSU:DAT Sr P S tHD:STA tSU:…

  • 324, Epson S1C31D50 21 HW Processor (HWP) and Sound Output 21-12 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) When the playback output is resumed, a smoothing (fade-in) process for the playback output signal is car- ried out to suppress the occurrence of noise due to a sudden rise of the signal. (See Fi…

  • 157, Epson S1C31D50 13 UART (UART3) 13-4 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) UART3_nMOD register PREN bit 0 1 0 1 0 1 0 1 STPB bit 0 0 1 1 0 0 1 1 CHLN bit 0 0 0 0 1 1 1 1 st: start bit, sp: stop bit, p: parity bit st D0 D1 D2 D3 D4 D5 D6 sp st D0 D1 D2 D3 D4 D5 D6 p sp st D0 D1 D2 D3 D4 D5 D6…

  • 26, 1 OVERVIEW S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 1-11 (Rev. 2.00) Pin name Assigned signal I/O Initial state Tolerant fail-safe structure Function Package 48-pin 64-pin 80-pin 100-pin PD1 SWD I/O I (Pull-up) ✓ Serial-wire debugger data input/output ✓ ✓ ✓ ✓ PD1 I/O I/O port PD2 …

  • 29, Epson S1C31D50 2 POWER SUPPLY, RESET, AND CLOCKS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 2-3 (Rev. 2.00) Notes: • After the voltage mode has been switched, correct the RTC, as the RTC operating clock is also stopped for the period set using the CLGOSC1.OSC1WT[1:0] bits. • Always use the IC in mode0 w…

  • 296, 19 12-BIT A/D CONVERTER (ADC12A) 19-6 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Table 19.4.4.1 DMA Data Structure Configuration Example (Capture Data Transfer) Item Setting example End pointer Transfer source ADC12A_nADD register address Transfer destination Memory address to …

  • 367, APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation AP-A-3 (Rev. 2.00) Address Register name Bit Bit name Initial Reset R/W Remarks 0x0020 00a4 WDT2CMP (WDT2 Counter Com- pare Match Register) 15–10 – 0x00 – R – 9–0 CMP[9:0] 0x3ff H0 R…

  • 248, Epson S1C31D50 17 16-BIT PWM TIMERS (T16B) 17-2 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Counter block Ch.0 Comparator/capture block Ch.0 Comparator/capture block Ch. n Comparator/capture circuits 0 & 1 Counter TC[15:0] MAX counter data register MC[15:0] CNTMD[1:0] ONEST RUN PRESET CLK_T16B0 CL…

  • 217, 15 Quad Synchronous Serial Interface (QSPI) 15-32 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) QSPI Ch.n Transmit Data Register Register name Bit Bit name Initial Reset R/W Remarks QSPI_nTXD 15–0 TXD[15:0] 0x0000 H0 R/W – Bits 15–0 TXD[15:0] Data can be written …

  • 405, Epson S1C31D50 APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation AP-A-41 (Rev. 2.00) 0x0020 0600–0x0020 0614 UART (UART3) Ch.1 Address Register name Bit Bit name Initial Reset R/W Remarks 0x0020 0600 UART3_1CLK (UART3 Ch.1 Clock Control Register) 15–9 – 0x00 �…

  • 210, 15 Quad Synchronous Serial Interface (QSPI) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 15-25 (Rev. 2.00) Table 15.5.6.1 DMA Data Structure Configuration Example (for 32-bit Sequential Read in Memory Mapped Access Mode) Item Setting example End pointer Transfer source External Flash memor…

  • 352, 22 ELECTRICAL CHARACTERISTICS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 22-11 (Rev. 2.00) SVD circuit current - power supply voltage characteristic Ta = 25°C, SVD3CTL.SVDC[4:0] bits = 0x04, CLK_SVD3 = 32 kHz, Typ. value 012 3 4 5 6 25 20 15 10 5 0 V DD [ V ] I SVD [µA] SVD3CTL.SVDMD[1:0…

  • 265, Epson S1C31D50 17 16-BIT PWM TIMERS (T16B) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 17-19 (Rev. 2.00) 4 5 3 2 1 0 5 4 3 2 1 0 5 4 3 2 RUN PRESET Count clock T16B_nTC.TC[15:0] MATCH signal ZERO signal T16B_nCCCTLm.TOUTO TOUT output ( * ) Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mod…

  • 293, Epson S1C31D50 19 12-BIT A/D CONVERTER (ADC12A) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 19-3 (Rev. 2.00) For the RADIN and CADIN values in the equivalent circuit, refer to “12-bit A/D Converter Characteristics” in the “Electrical Characteristics” chapter. Based on these values, configure the ADC1…

  • 127, 10 REAL-TIME CLOCK (RTCA) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 10-3 (Rev. 2.00) Notes: • The theoretical regulation affects only the real-time clock counter and 1 Hz counter. It does not affect the stopwatch counter. • After a value is written to the RTCACTLH.RTCTRM[6…

  • 385, APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation AP-A-21 (Rev. 2.00) Address Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 100 pin 0x0020 027c P7MODSEL (P7 Port Mode Select Register) 15–8 – 0x00 – R – – – – –…

  • 331, 21 HW Processor (HWP) and Sound Output S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 21-19 (Rev. 2.00) Bits 15–4 Reserved Set to 0x000 when writing data to this register. Bit 3 TO_MUTE Bit 2 TO_PAUSE Bit 1 TO_PLAY Bit 0 TO_IDLE These bits set whether the interrupt request when a state transitio…

  • 16, 1 OVERVIEW S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 1-1 (Rev. 2.00) 1 Overview 1.1 Features The S1C31D50/D51 is a 32-bit Arm ® Cortex ® -M0+ MCU, which integrates a specific hardware block called the HW Processor. The HW Processor can perform 2-channel Voice/Audio playback, Voice Speed Conversion,…

  • 39, Epson S1C31D50 2 POWER SUPPLY, RESET, AND CLOCKS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 2-13 (Rev. 2.00) OSC1 oscillation stop detection function The oscillation stop detection function restarts the OSC1 oscillator circuit when it detects oscillation stop under adverse environments that may stop the osc…

  • 164, 13 UART (UART3) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 13-11 (Rev. 2.00) 13.9 Control Registers UART3 Ch.n Clock Control Register Register name Bit Bit name Initial Reset R/W Remarks UART3_nCLK 15–9 – 0x00 – R – 8 DBRUN 0 H0 R/W 7–6 – 0x0 – R 5–4 CLKDIV[1:0] 0x0 H0 R/W 3–2 –…

  • 208, Epson S1C31D50 15 Quad Synchronous Serial Interface (QSPI) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 15-23 (Rev. 2.00) n 2 0/1 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA #QSPISSn QSPICLKn QSDIOn[3:0] #QSPISSn inactive period (TCSH) QSPI_ nMOD register CPHA bit 1 0 CPOL bit 1 0 n HCLK HSEL HADDR HTRANS HSIZE HREADY …

  • 197, 15 Quad Synchronous Serial Interface (QSPI) 15-12 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) - QSPI_nMMACFG2.DUMDL[3:0] bits (Select dummy cycle drive length) - QSPI_nMMACFG2.DUMLN[3:0] bits (Select dummy cycle length) - QSPI_nMMACFG2.DATTMOD[1:0] bits (Select data cycle tra…

  • 92, Epson S1C31D50 7 I/O PORTS (PPORT) 7-14 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 100 pin P0MODSEL (P0 Port Mode Select Register) 15–8 – 0x00 – R – – – – – 7 P0SEL7 0 H0 R/W – – – ✓ ✓ 6 P0…

  • 12, CONTENTS x Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) REMC3 Data Bit Length Register ........................................................................................ 18-10 REMC3 Status and Interrupt Flag Register .......................................................…

  • 163, 13 UART (UART3) 13-10 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) 13.7 Interrupts The UART3 has a function to generate the interrupts shown in Table 13.7.1. Table 13.7.1 UART3 Interrupt Function Interrupt Interrupt flag Set condition Clear condition End of transmission UAR…

  • 184, 14 SYNCHRONOUS SERIAL INTERFACE (SPIA) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 14-15 (Rev. 2.00) SPIA Ch.n Transmit Data Register Register name Bit Bit name Initial Reset R/W Remarks SPIA_nTXD 15–0 TXD[15:0] 0x0000 H0 R/W – Bits 15–0 TXD[15:0] Data can be written to the transmit data buffer …

  • 109, 7 I/O PORTS (PPORT) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 7-31 (Rev. 2.00) 7.7.9 P8 Port Group The P8 port group supports the GPIO and interrupt functions. Table 7.7.9.1 Control Registers for P8 Port Group Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 10…

  • 310, 20 R/F CONVERTER (RFC) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 20-9 (Rev. 2.00) Bit 7 CONEN This bit disables the automatic CR oscillation stop function to enable continuous oscillation function. 1 (R/W): Enable continuous oscillation 0 (R/W): Disable continuous oscillation For …

  • 30, 2 POWER SUPPLY, RESET, AND CLOCKS 2-4 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) 2.2.2 Input Pin Table 2.2.2.1 shows the SRC pin. Table 2.2.2.1 SRC Pin Pin name I/O Initial status Function #RESET I I (Pull-up) Reset input The #RESET pin is connected to the noise filter that removes …

  • 106, 7 I/O PORTS (PPORT) 7-28 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 100 pin P6MODSEL (P6 Port Mode Select Register) 15–8 – 0x00 – R – – – – – 7 P6SEL7 0 H0 R/W – – – – ✓ 6 P6SEL6…

  • 187, Epson S1C31D50 15 Quad Synchronous Serial Interface (QSPI) 15-2 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) QSPI Ch.n Timer CPU core Clock/shift register control circuit Pull-up/down control circuit I/O and slave select control circuit 16-bit timer Underflow Receive data buffer RXD[15:0] Trans…

  • 171, Epson S1C31D50 14 SYNCHRONOUS SERIAL INTERFACE (SPIA) 14-2 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) 14.2 Input/Output Pins and External Connections 14.2.1 List of Input/Output Pins Table 14.2.1.1 lists the SPIA pins. Table 14.2.1.1 List of SPIA Pins Pin name I/O* Initial status* Function SDIn I …

  • 70, 6 DMA CONTROLLER (DMAC) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 6-7 (Rev. 2.00) 6.5.4 Memory Scatter-Gather Transfer In scatter-gather transfer mode, first the DMAC, using the primary data structure, copies a data structure from the data structure table, which has been prepared with multi…

  • 185, Epson S1C31D50 14 SYNCHRONOUS SERIAL INTERFACE (SPIA) 14-16 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) The following shows the correspondence between the bit and interrupt: SPIA_nINTF.OEIF bit: Overrun error interrupt SPIA_nINTF.TENDIF bit: End-of-transmission interrupt SPIA_nINTF.RBFIF bit:…

  • 357, 22 ELECTRICAL CHARACTERISTICS 22-16 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) RFC reference/sensor oscillation frequency- RFC reference/sensor oscillation current temperature characteristic consumption-frequency characteristic RREF/RSEN = 100 kW, CREF = 1,000 pF, Typ. value …

  • 33, Epson S1C31D50 2 POWER SUPPLY, RESET, AND CLOCKS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 2-7 (Rev. 2.00) IOSC oscillator circuit Internal data bus IOSCEN Clock oscillator Oscillation stabilization waiting circuit Interrupt control circuit IOSCFQ[1:0] IOSCSTAIE IOSCSTAIF CPU core IOSCCLK Figure 2.3.3.1 IOSC …

  • 136, 10 REAL-TIME CLOCK (RTCA) 10-12 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Table 10.6.2 Correspondence between the count value and day of the week RTCAYAR.RTCWK[2:0] bits Day of the week 0x6 Saturday 0x5 Friday 0x4 Thursday 0x3 Wednesday 0x2 Tuesday 0x1 Monday 0x0 Sunday Note:…

  • 110, 7 I/O PORTS (PPORT) 7-32 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 100 pin P8INTF (P8 Port Interrupt Flag Register) 15–8 – 0x00 – R – – – – – 7 P8IF7 0 H0 R/W Cleared by writing 1…

  • 250, Epson S1C31D50 17 16-BIT PWM TIMERS (T16B) 17-4 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) 17.4 Operations 17.4.1 Initialization T16B Ch.n should be initialized and started counting with the procedure shown below. Perform initial settings for comparator mode when using T16B as an interval…

  • 272, 17 16-BIT PWM TIMERS (T16B) 17-26 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Bits 15–0 TC[15:0] The current counter value can be read out through these bits. T16B Ch.n Counter Status Register Register name Bit Bit name Initial Reset R/W Remarks T16B_nCS 15–8 – 0x00 – R �…

  • 47, 2 POWER SUPPLY, RESET, AND CLOCKS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 2-21 (Rev. 2.00) CLG Interrupt Flag Register Register name Bit Bit name Initial Reset R/W Remarks CLGINTF 15–9 – 0x00 – R – 8 OSC3TERIF 0 H0 R/W Cleared by writing 1. 7 – 0 – R – 6 (reserved) 0 H0 R …

  • 190, 15 Quad Synchronous Serial Interface (QSPI) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 15-5 (Rev. 2.00) #QSPISSn QSDIOn1 QSDIOn0 QSPICLKn #SPISS0 #SPISS1 #SPISS2 SDIO1 SDIO0 SPICK S1C31 QSPI (slave mode) #SPISS SDIO1 SDIO0 SPICK #SPISS SDIO1 SDIO0 SPICK External dual-I/O SPI slave devices External dua…

  • 73, Epson S1C31D50 6 DMA CONTROLLER (DMAC) 6-10 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) 6.8 Control Registers DMAC Status Register Register name Bit Bit name Initial Reset R/W Remarks DMACSTAT 31–24 – 0x00 – R – 23–21 – 0x0 – R 20–16 CHNLS[4:0] * H0 R * Number of channels im…

  • 394, APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS AP-A-30 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Address Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 100 pin 0x0020 031e UPMUXP3MUX3 (P36 Universal Port Multiplexer Setting Registe…

  • 416, Epson S1C31D50 APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS AP-A-52 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Address Register name Bit Bit name Initial Reset R/W Remarks 0x0020 0844 RFC_0TRG (RFC Ch.0 Oscillation Trigger Register) 15–8 – 0x00 – R – 7–3 – 0…

  • 234, 16 I 2 C (I2C) 16-12 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Data sending operations START condition detection and slave address check While the I2C_nCTL.MODEN bit = 1 and the I2C_nCTL.MST bit = 0 (slave mode), the I2C Ch.n monitors the I 2 C bus. When the I2C Ch.n det…

  • 354, Epson S1C31D50 22 ELECTRICAL CHARACTERISTICS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 22-13 (Rev. 2.00) 22.11 Quad Synchronous Serial Interface (QSPI) Characteristics Master mode Unless otherwise specified: VDDQSPI = 3.0 to 3.6 V, VSS = 0 V, Ta = -40 to 85°C Item Symbol Condition VD1 output Min. Typ. Max. 単位 …

  • 100, 7 I/O PORTS (PPORT) 7-22 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 100 pin P4IOEN (P4 Port Enable Register) 15 P4IEN7 0 H0 R/W – – – – ✓ 14 P4IEN6 0 H0 R/W ✓ ✓ ✓ ✓ 13 P4IEN5 0 H0 R/W ✓ ✓ …

  • 317, Epson S1C31D50 21 HW Processor (HWP) and Sound Output S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 21-5 (Rev. 2.00) 4. Set the SDACDAT.DAT[9:0] bits to 0x000. (Clear sound data register) 5. Disable SDAC interrupts to occur. - Set the SDACINTE register to 0x0000. (Disable interrupts) - Write 0x0003 to the SDACINTF …

  • 98, Epson S1C31D50 7 I/O PORTS (PPORT) 7-20 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 100 pin P3RCTL ( P3 Port Pull-up/down Control Register ) 15 P3PDPU7 0 H0 R/W – – – – ✓ 14 P3PDPU6 0 H0 R/W – – – ✓ 13 P3PD…

  • 78, 6 DMA CONTROLLER (DMAC) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 6-15 (Rev. 2.00) Bit 0 ERRIESET This bit enables DMA error interrupts. 1 (W): Enable interrupt 0 (W): Ineffective 1 (R): Interrupt has been enabled. 0 (R): Interrupt has been disabled. DMAC Error Interrupt Enable Clear R…

  • 260, 17 16-BIT PWM TIMERS (T16B) 17-14 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) (3.2) T16B_nCCCTLm.CBUFMD[2:0] bits = 0x1 CNTZEROIF = 1 0xffff 0x0000 RUN = 1 Data (W) → MC[15:0] Data (W) → CC[15:0] Data (W) → CC[15:0] Data (W) → CC[15:0] MODEN = 1 CMPCAPmIF =…

  • 309, Epson S1C31D50 20 R/F CONVERTER (RFC) 20-8 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) 20.6 Control Registers RFC Ch.n Clock Control Register Register name Bit Bit name Initial Reset R/W Remarks RFC_nCLK 15–9 – 0x00 – R – 8 DBRUN 1 H0 R/W 7–6 – 0x0 – R 5–4 CLKDIV[1:0] 0x0 H0…

  • 55, 4 MEMORY AND BUS 4-6 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Peripheral circuit Address Register name Synchronous serial interface (SPIA) Ch.0 0x0020 03b8 SPIA_0INTF SPIA Ch.0 Interrupt Flag Register 0x0020 03ba SPIA_0INTE SPIA Ch.0 Interrupt Enable Register 0x0020 03bc SPIA_0TB…

  • 25, 1 OVERVIEW 1-10 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Pin name Assigned signal I/O Initial state Tolerant fail-safe structure Function Package 48-pin 64-pin 80-pin 100-pin P51 SDACOUT_N O O (L) ✓ Sound DAC nagetive output ✓ ✓ ✓ ✓ P51 I/O I/O port P5…

  • 124, Epson S1C31D50 9 WATCHDOG TIMER (WDT2) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 9-5 (Rev. 2.00) Bits 9–0 CMP[9:0] These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they …

  • 20, 1 OVERVIEW S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 1-5 (Rev. 2.00) QFP13-64PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30 P31 P32 P33 P34 VPP P90 P91 P92 P93 P94 P95 VDDQSPI PA1 PA2 PA3 P30/RFCLKO0/UPMUX P31/REMO/UPMUX P32/CLPLS/UPMUX P33/UPMUX P3…

  • 93, Epson S1C31D50 7 I/O PORTS (PPORT) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 7-15 (Rev. 2.00) Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 100 pin P1IOEN (P1 Port Enable Register) 15 P1IEN7 0 H0 R/W – ✓ ✓ ✓ ✓ 14 P1IEN6 0 H0 R/W ✓ ✓ ✓ ✓ 13 P1IEN5 0 H0 R/W ✓…

  • 411, APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation AP-A-47 (Rev. 2.00) Address Register name Bit Bit name Initial Reset R/W Remarks 0x0020 06c2 I2C_1MOD (I2C Ch.1 Mode Register) 15–8 – 0x00 – R – 7–3 – 0x00 – R 2 OADR10 0 H0 R/W 1 GCEN 0…

  • 307, Epson S1C31D50 20 R/F CONVERTER (RFC) 20-6 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) The time base counter overflow sets the RFC_nINTF.OVTCIF bit to 1 indicating that the reference oscil- lation has been terminated abnormally. If the RFC_nINTE.OVTCIE bit = 1, a time base counter overflow error in…

  • 132, Epson S1C31D50 10 REAL-TIME CLOCK (RTCA) 10-8 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Bits 14–12 RTCSHA[2:0] Bits 11–8 RTCSLA[3:0] The RTCAALM1.RTCSHA[2:0] bits and the RTCAALM1.RTCSLA[3:0] bits set the 10-second digit and 1-second digit of the alarm time, respectively. A value w…

  • 24, 1 OVERVIEW S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 1-9 (Rev. 2.00) Pin name Assigned signal I/O Initial state Tolerant fail-safe structure Function Package 48-pin 64-pin 80-pin 100-pin P15 P15 I/O Hi-Z – I/O port ✓ ✓ ✓ ✓ UPMUX I/O User-selected I/O (universal port multiplexe…

  • 74, 6 DMA CONTROLLER (DMAC) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 6-11 (Rev. 2.00) DMAC Control Data Base Pointer Register Register name Bit Bit name Initial Reset R/W Remarks DMACCPTR 31–0 CPTR[31:0] 0x0000 0000 H0 R/W – Bits 31–0 CPTR[31:0] These bits set the leading address of the da…

  • 170, 14 SYNCHRONOUS SERIAL INTERFACE (SPIA) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 14-1 (Rev. 2.00) 14 Synchronous Serial Interface (SPIA) 14.1 Overview SPIA is a synchronous serial interface. The features of SPIA are listed below. • Supports both master and slave modes. • Data leng…

  • 300, 19 12-BIT A/D CONVERTER (ADC12A) 19-10 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) ADC12A Ch.n Interrupt Flag Register Register name Bit Bit name Initial Reset R/W Remarks ADC12A_nINTF 15–9 – 0x00 – R – 8 OVIF 0 H0 R/W Cleared by writing 1. 7 AD7CIF 0 H0 R/W 6 AD6CIF 0 H0 R/W 5…

  • 326, Epson S1C31D50 21 HW Processor (HWP) and Sound Output 21-14 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) 1) hwp_sleep After the MCU boots up, the HWP enters this state (HWPCTL.HWPEN bit = 0). In this state, the clock supply to the HWP stops. By setting the HWPCTL.HWPEN bit to 1 after con…

  • 299, 19 12-BIT A/D CONVERTER (ADC12A) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 19-9 (Rev. 2.00) Bits 5–4 CNVTRG[1:0] These bits select a trigger source to start A/D conversion. Table 19.7.2 Trigger Source Selection ADC12A_nTRG.CNVTRG[1:0] bits Trigger source 0x3 #ADTRGn pin (external trig…

  • 325, 21 HW Processor (HWP) and Sound Output S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 21-13 (Rev. 2.00) 21.4.2 Memory Check Function Initialization Before using the memory check function, initialize the HWP as shown below. 1. Configure the HWP operating clock as necessary. (Refer to “Clock Settings…

  • 423, APPENDIX D MEASURES AGAINST NOISE S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation AP-D-1 (Rev. 2.00) Appendix D Measures Against Noise To improve noise immunity, take measures against noise as follows: Noise Measures for VDD, VDDQSPI, and VSS Power Supply Pins When noise falling below the rated vol…

  • 205, 15 Quad Synchronous Serial Interface (QSPI) 15-20 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) n 2 2 2 0 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA fifo_read_level #QSPISSn QSPICLKn QSDIOn[3:0] #QSPISSn inactive period (TCSH) QSPI_ nMOD register CPHA bit 1 0 CPOL bit 1 0 0 1 0 n HCLK HS…

  • 85, 7 I/O PORTS (PPORT) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 7-7 (Rev. 2.00) Interrupt check in port group unit When interrupts are enabled in two or more port groups, check the PPORTINTFGRP.PxINT bit in the interrupt handler first. It helps minimize the handler codes for finding the port that has g…

  • 361, Epson S1C31D50 24 PACKAGE S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 24-1 (Rev. 2.00) 24 Package TQFP12-48PIN (P-TQFP048-0707-0.50) 7 9 2536 7 9 13 24 INDEX 0.17min/0.27max 121 48 37 10.1 1.2 max 1 0.3 min/0.7max 0°min/10° max 0.09min/0.2max 0.5 Figure 24.1 TQFP12-48PIN Package Dimensions …

  • 5, CONTENTS S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation iii (Rev. 2.00) 4.3.1 Flash Memory Pin ................................................................................................... 4-2 4.3.2 Flash Bus Access Cycle Setting........................................................…

  • 384, Epson S1C31D50 APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS AP-A-20 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Address Register name Bit Bit name Initial Reset R/W Remarks 48 pin 64 pin 80 pin 100 pin 0x0020 0274 P7RCTL ( P7 Port Pull-up/down Control Register ) 15 P7PDPU7 …

  • 282, Epson S1C31D50 18 IR REMOTE CONTROLLER (REMC3) 18-4 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Carrier signal Data signal (Modulated data) REMO output REMC3CCTL. REMC3DBCTL. OUTINVEN bit  REMOINV bit 0 0 0 1 1 0 1 1 Data bit Figure 18.4.3.1 REMO Output Waveform Ex…

  • 267, 17 16-BIT PWM TIMERS (T16B) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 17-21 (Rev. 2.00) RUN PRESET Count clock T16B_nTC.TC[15:0] MATCH(0) signal MATCH(1) signal T16B_nCCCTLm.TOUTO TOUT output ( * ) Software control mode (0x0) TOUTn0 TOUTn1 Set mode (0x1) TOUTn0 TOUTn1 Toggle/reset mode (0x2) TOUTn0 TOUTn…

  • 162, 13 UART (UART3) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 13-9 (Rev. 2.00) The carrier modulation output frequency is determined by the UART3_nCAWF.CRPER[7:0] bit settings. Use the following equations to calculate the setting values for obtaining the desired frequency. CLK_UART3 Carrier modulation outp…

  • 188, Epson S1C31D50 15 Quad Synchronous Serial Interface (QSPI) S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation 15-3 (Rev. 2.00) #QSPISSn QSDIOn3 QSDIOn2 QSDIOn1 QSDIOn0 QSPICLKn #QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK S1C31 QSPI (memory mapped access mode) External QSPI slave device Figure 15.2.2.1 Connections betwe…

  • 138, 10 REAL-TIME CLOCK (RTCA) 10-14 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) Bits 11–9 Reserved Bit 8 ALARMIE Bit 7 T1DAYIE Bit 6 T1HURIE Bit 5 T1MINIE Bit 4 T1SECIE Bit 3 T1_2SECIE Bit 2 T1_4SECIE Bit 1 T1_8SECIE Bit 0 T1_32SECIE These bits enable real-time clock inte…

  • 42, 2 POWER SUPPLY, RESET, AND CLOCKS 2-16 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL (Rev. 2.00) CLG System Clock Control Register Register name Bit Bit name Initial Reset R/W Remarks CLGSCLK 15 WUPMD 0 H0 R/WP – 14 – 0 – R 13–12 WUPDIV[1:0] 0x0 H0 R/WP 11–10 – 0x0 – R 9…

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