Xilinx 7 Series Operation & User’s Manual

77, 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 77 UG482 (v1.9) December 19, 2016 FPGA TX Interface TXUSRCLK and TXUSRCLK2 Generation The FPGA TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2. TXUSRCLK is the internal clock for the PCS logic in the GTP transceiv…

140, 140 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide UG482 (v1.9) December 19, 2016 Chapter 4: Receiver Table 4-10: RX Equalizer Attributes Attribute Type Description ADAPT_CFG0 20-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard should …

303, Xilinx 7 Series 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 303 UG482 (v1.9) December 19, 2016 009C (Cont’d) 5:0 R/W RXBUF_THRESH_UNDFLW 5:0 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 59 60 60 61 61 62 …

41, 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 41 UG482 (v1.9) December 19, 2016 Reset and Initialization PLL Reset The PLLs (PLL0 and PLL1) must be powered down using the PLL0PD and PLL1PD ports until reference clock edges are detected in the logic. After PLL0PD/PLL1PD is de-asse…

162, 162 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide UG482 (v1.9) December 19, 2016 Chapter 4: Receiver Figure 4-29 shows how a comma is combined with ALIGN_COMMA_ENABLE to make a wild-carded comma for a 20-bit internal comma. If ALIGN_COMMA_DOUBLE is TRUE, the MCOMMA and PCOMMA patte…

17, 7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 17 UG482 (v1.9) December 19, 2016 Simulation SecureIP models are encrypted versions of the Verilog HDL used for implementation of the modeled block. SecureIP is an IP encryption methodology. To support SecureIP models, a Ve…