AMD Geode LX CS5536 Manual 

1, 46959A - March 2009 1 AMD Geode™ LX Processor DDR2 BIOS Porting Guide 1.0 Scope The AMD Geode™ LX processor has an integrated DDR memory controller. Due to the concerns over the availability and increasing cost of DDR, AMD has developed a method for operating DDR2 memory with the p…

8, © 2009 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this p…

3, AMD Geode™ LX Processor DDR2 BIOS Porting Guide 3 46959A - March 2009 Application Note 3.2 CPLD Registers The CPLD contains two registers that indicate how it should assert the BA[1:0], A[12:0] signals and switch enable signals. • If accessing the registers via I2C, the regi…

4, AMD Geode LX CS5536 4 AMD Geode™ LX Processor DDR2 BIOS Porting Guide 46959A - March 2009 Application Note 3.3 Initialization Steps Some of the following steps may be optional, depending on the specific implementation. The reader is encouraged to have a copy of the JEDEC standard for DDR2 SDRAM, includin…

5, AMD Geode™ LX Processor DDR2 BIOS Porting Guide 5 46959A - March 2009 Application Note cally supportable. As an example, consider the follow- ing DIMM characteristics: This is has a fundamental access time of 15ns, and therefore at CL=2, the minimum cycle time should be 7.5ns. T…