Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Hardware Manual for Hitachi H8S/2378, H8S/2378R Series Computer Hardware (949 pages)

Specifications:

940/940375-h8s2378_h8s2378r_series.pdf file (30 Sep 2023)

Manufacturer: Hitachi
Category of Device: Computer Hardware
Document: H8S/2378, H8S/2378R Series, File Type: PDF Hardware Manual
Updated: 30-09-2023
Count of Pages: 949

Download H8S/2378, H8S/2378R Series Manual (949 pages)

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Data: UPD 30th September 2023

Hitachi H8S/2378, H8S/2378R Series Computer Hardware PDF Hardware Manual (Updated: Saturday 30th of September 2023 03:56:32 AM)

Rating: 4.1 (rated by 6 users)

Compatible devices: Travelstar Z5K320 HTS543232A7A384, H8/3022 F-ZTAT, H8/3152, HD6473867, H8/3048, H8S/2215 Series, G-SPEED ES PRO, H8/3664.

Text Version of Hitachi H8S/2378, H8S/2378R Series Computer Hardware Manual (Summary of Contents)

(Ocr-Read of Hitachi H8S/2378, H8S/2378R Series Document (Main Content), UPD: 30 September 2023)

103, Rev. 1.0, 09/01, page 59 of 904 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.4 show memory maps for each product. Mode 1 and 2 (Expanded mode with on-chip ROM disabled) Mode 3 (Boot mode) H'000000 H'FF4000 H'FF6000 H'FFC000 H'FFC800 H'000000 H'FF…
318, Rev. 1.0, 09/01, page 274 of 904 Address T Address B Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L Address B = L + (–1) DTID · (2 DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential…
472, Rev. 1.0, 09/01, page 428 of 904 • P20/PO0/TIOCA3/( ,54;, The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL, bit P2…
797, Rev. 1.0, 09/01, page 753 of 903 Section 18 D/A Converter 18.1 Features D/A converter features are listed below. • 8-bit resolution • Six output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to Vref • D/A output hold function in so…
171, Rev. 1.0, 09/01, page 127 of 904 Bit Bit Name Initial Value R/W Description 011: 11-bit shift • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM…
813, Hitachi H8S/2378, H8S/2378R Series Rev. 1.0, 09/01, page 769 of 904 Flash memory This LSI RAM Host Programming/ erase control program SCI Boot program New application program Flash memory This LSI RAM Host SCI New application program Flash memory This LSI RAM Host SCI Flash memory erase Boot program New application program Flash me…

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