Specifications:924/924255-axel_lite.pdf file (08 Dec 2023)
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Dave Embedded Systems AXEL LITE Computer Hardware PDF Hardware Manual (Updated: Friday 8th of December 2023 09:37:23 AM)
Rating: 4.8 (rated by 29 users)
Compatible devices: diDo, AM4500, ARM Cortex-A9 MPCore, Profile 4, IBG4-MEM-CIP1, CP1L, RM7895 Series, 299B.
Recommended Documentation:
40, AXEL LITE Hardware Manual v. 0.9.5 Pin name Conn. Pin Function Notes ETH0_TXRX0_M J2.21 Media Dependent Interface[0], negative pin ETH0_TXRX1_P J2.23 Media Dependent Interface[1], positive pin ETH0_TXRX1_M J2.25 Media Dependent Interface[1], negative pin ETH0_TXRX2_P J2.27 Media Dependent …
31, Dave Embedded Systems AXEL LITE AXEL LITE Hardware Manual v. 0.9.5 6.1 Carrier board mating connector J2 J2 – ODD [1-203] Pin Pin Name Internal Connections Ball/ pin # Supply Group Type Voltage Note J2.1 DGND DGND - J2.3 3.3VIN INPUT VOLTAGE J2.5 3.3VIN INPUT VOLTAGE J2.7 3.3VIN INPUT VOLTAGE J2.9 3.3VIN INPUT VOLT…
57, AXEL LITE Hardware Manual v. 0.9.5 Pin name Conn. Pin Function Notes SD3_DATA5 J2.49 DATA5 line in 8-bit mode, not used in other modes SD3_DATA6 J2.51 DATA6 line in 8-bit mode, not used in other modes SD3_DATA7 J2.53 DATA7 line in 8-bit mode, not used in other modes SD3_RST J2.37 Card hard…
58, AXEL LITE Hardware Manual v. 0.9.5 7.15 GPIO The i.MX6 GPIO module provides general-purpose pins that can be configured as either inputs or outputs, for connections to external devices. In addition, the GPIO peripheral can produce CORE interrupts. The device contains eight GPIO blocks a…
56, AXEL LITE Hardware Manual v. 0.9.5 Pin name Conn. Pin Function Notes SD2_DATA3 J2.67 DATA3 line in 4/8-bit mode or configured as card detection pin May be configured as card detection pin in 1-bit mode SD2_LCTL J2.40 LED control used to drive an external LED Active high Fully controlled by…
19, AXEL LITE Hardware Manual v. 0.9.5 Size min 16 MByte Size max 64 MByte Chip select ECSPI1_SS0 Bootable Yes Tab. 8: NOR flash specifications For AXEL LITE models that have the NOR flash bank populated, the eCSPI channel 1 is mapped by design on the following multiplexed pins: NOR s…
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