Analog Devices AD9883A Manual, Specification Sheet

14, REV. 0 AD9883A –14– Table VI. Control Register Map (continued) Write and Hex Read or Default Register Address Read Only Bits Value Name Function 0FH R/W 7:1 0******* Bit 7 – Clamp Function. Chooses between HSYNC for Clamp signal or another external signal to be used for clamping. (Logic 0 …

11, Analog Devices AD9883A REV. 0 AD9883A –11– Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Refresh Horizontal Standard Resolution Rate Frequency Pixel Rate VCORNGE Current VGA 640 × 480 60 Hz 31.5 kHz 25.175 MHz 00 101 72 Hz 37.7 kHz 31.500 MHz 00 110 75 Hz 37.5 kHz 31.50…

16, REV. 0 AD9883A –16– 04 7–3 Clock Phase Adjust A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25° shift in sampling phase. The power-up default value is 16. CLAMP TIMING 05 7–0 Clamp Placement An 8-bit register that se…

17, REV. 0 AD9883A –17– 0E 5 Hsync Output Polarity One bit that determines the polarity of the Hsync output and the SOG output. Table XI shows the effect of this option. SYNC indicates the logic state of the sync pulse. Table XI. Hsync Output Polarity Settings Setting SYNC 0 Logic 1 (Positive Polari…

12, REV. 0 AD9883A –12– P0 P1 P2 P3 P4 P5 P6 P7 5-PIPE DELAY D0 D1 D2 D3 D4 D5 D6 D7 RGB IN HSYNC PxCK HS ADCCK DATACK D OUTA HSOUT VARIABLE DURATION Figure 8. 4:4:4 Mode (For RGB and YUV) P0 P1 P2 P3 P4 P5 P6 P7 5-PIPE DELAY Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 RGB IN HSYNC PxCK HS ADCCK DATACK G OUTA HS…

6, REV. 0 AD9883A –6– PIN FUNCTION DESCRIPTIONS Pin Name Function OUTPUTS HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK, and Da…