Janz Tec emPC-CXR Hardware Manual

28, 6 - 26 emPC-CXR (Hardware Manual) • FPGA expansion subsystem © Janz Tec AG Rev. V1.2 I2C_CONTROL BAR4 + 0x1c (32bit, rw) 31..10 9 8 7..2 1 0 reserved SCL SDA SDA I 2 C bidirectional data line. Writing 0 sets the data line to low potential. Writing 1 …

33, Janz Tec emPC-CXR emPC-CXR (Hardware Manual) • System Control 7 - 31 Rev. V1.2 © Janz Tec AG 7 System Control The emPC-CXR provides some features for system control and supervision. Refer to figure 3 for the relevant components: • The system MCU which controls the power supply and C…

17, emPC-CXR (Hardware Manual) • Installation 3 - 15 Rev. V1.2 © Janz Tec AG Each port pin (DIO1…DIO4) is able to source 500mA into a load. The sum of all output currents should be limited to 1A. NOTICE When outputs are turned on, they source power f…

12, 3 - 10 emPC-CXR (Hardware Manual) • Installation © Janz Tec AG Rev. V1.2 NOTICE The ambient temperatures below, left, right and in front of the product must not exceed the specified maximum ambient temperature. 3.1.1 Mounting Screws The product must be moun…

18, 3 - 16 emPC-CXR (Hardware Manual) • Installation © Janz Tec AG Rev. V1.2 3.3 Application Hints 3.3.1 Right Angle Cable When using right angle M8/M12 connectors, you have to obey the exit direction of the cables when planning the cabling. In figure 6 you find an example with …

31, emPC-CXR (Hardware Manual) • FPGA expansion subsystem 6 - 29 Rev. V1.2 © Janz Tec AG 6.5 Digital IO Programming the digital IO is utilized by reading/writing register in the FPGA register space. Address Offset access Description BAR5 + 0x00 - - BAR5 + 0x01…