Specifications:1302/1302445-pciebiserialdb37lm9.pdf file (20 Nov 2023)
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Dynamic Engineering PCIeBiSerialDb37-LM9 PCI Card PDF Operation & User’s Manual (Updated: Monday 20th of November 2023 12:26:32 AM)
Rating: 4.3 (rated by 20 users)
Compatible devices: PCM-2604C-AE, PCIe 8L XMC X1, PCI2PMC, PCIe8LSwVPX3U, LVDS 8R, PCIe8LXMCX2CB, CINERGY 2400 I DT MCE edition, AO-1616L-LPE.
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9, Embedded Solutions Page 9 The transmitter and receiver have 4K x 32 FIFO’s with direct access, DMA support, and loop-back capabilities. The driver/reference software includes examples of all three modes. DMA when used will keep the transmi…
43, Embedded Solutions Page 43 Order Information standard temperature range Industrial PcieBiSerialDb37Lm9 PMC Module with 22 IO channels. One Transmitter and one Receiver port implemented. http://www.dyneng.com/pciebiserialdb37.ht…
14, Embedded Solutions Page 14 Programming Programming the PcieBiSerialDb37Lm9 requires only the ability to read and write data in the host's PCIe space. Once the initialization process has occurred, and the system has assigned addresses to the P…
12, Embedded Solutions Page 12 Address Map Function Offset // PCIeBiSerialDb37LM9 BASE definitions #define LM9_BASE_BASE 0x0000 // 0 LM9Base Base control register #define LM9_BASE_PLL_WRITE 0x0000 // 0 LM9Base Base control register #defi…
17, Embedded Solutions Page 17 The reference frequency for the PLL is 50 MHz. LM9_BASE_ID [$04 Switch and Design number port read only] DATA BIT DESCRIPTION 31-24 spare 23-8 Design ID and Revision 7-0 DIP switch Figure 6 PcieBiSerialDb37L…
21, Dynamic Engineering PCIeBiSerialDb37-LM9 Embedded Solutions Page 21 LM9_CHAN_STATUS [0x4] Channel Status Read/Clear Latch Write Port Channel Status Register Data Bit Description 31 Interrupt Status 30 LocalInt 29-28 Spare 27 RxPacketFull 26 RxPacketMt 25 TxPacketFull 24 TxPa…
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