Altera Cyclone V Manual, Device Handbook

995, Watchdog Timer Block Diagram and System Integration Each watchdog timer consists of a slave interface for control and status register (CSR) access, a register block, and a 32-bit down counter that operates on the slave interface clock (osc1_clk). A pause input, driven by the system manager, op…

641, The NAND flash controller performs the following initialization steps: 1. If the system manager is asserting bootstrap_inhibit_init, the flash controller goes directly to step 7. 2. When the device is ready, the flash controller sends the ONFI Read ID command to read the ONFI signature …

963, I 2 C controller contains a software programmable register, IC_SDA_HOLD, to enable dynamic adjustment of the SDA hold time. † DMA Controller Interface The I 2 C controller supports DMA signaling to indicate when data is ready to be read or when the transmit FIFO needs data. Thi…

303, Altera Cyclone V FunctionalityBlock • Recovers the clock and serial data stream if you configure the channel PLL as a CDR. • Requires offset cancellation to correct the analog offset voltages. • If you do not use the channel PLL as a CDR, you can configure the channel PLL as a CMU PLL for clocking …

856, DescriptionWidthIn/OutSignal Name PHY Receive Data Valid. This signal is driven by PHY and has multiple functions depending on which PHY interface is selected, as listed below: • GMII: When high, indicates that the data on the phy_rxd bus is valid. It remains asserted continuously from…

1002, Functional Description of the CAN Controller The CAN controllers perform communication according to the CAN protocol version 2.0 parts A and B. All communication on the CAN bus is through message objects. The CAN controller stores message objects in its internal message RAM. The host proce…