Analog Devices SHARC ADSP-21367 Manual 

15, ADSP-21367/ADSP-21368/ADSP-21369 Rev. D | Page 15 of 56 | November 2008 DATA MODES The upper 32 data pins of the external memory interface are muxed (using bits in the SYSCTL register) to support the exter- nal memory interface data (input/output), the PDAP (input only), the FLA…

27, ADSP-21367/ADSP-21368/ADSP-21369 Rev. D | Page 27 of 56 | November 2008 SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Table 24. SDRAM Interface Enable/Disable Timing 1 1 For f CCLK = 400 MHz (SDCLK ratio = 1:2.5). Parameter Min Max Unit Switching Characteristics t DSDC Comman…

52, Rev. D | Page 52 of 56 | November 2008 ADSP-21367/ADSP-21368/ADSP-21369 208-LEAD LQFP_EP PINOUT Table 47. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal 1V DDINT 43 V DDINT 85 V DDEXT 127 V DDINT 169 CL…

16, Rev. D | Page 16 of 56 | November 2008 ADSP-21367/ADSP-21368/ADSP-21369 SPECIFICATIONS OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS Parameter 1 1 Specifications subject to change without notice. Description 400 MHz 350 MHz 333 MHz 266 MHz Min Max Min Max Min Max Min Max Unit V DDINT Internal…

47, Analog Devices SHARC ADSP-21367 ADSP-21367/ADSP-21368/ADSP-21369 Rev. D | Page 47 of 56 | November 2008 Figure 41. Typical Output Rise/Fall Time (20% to 80%, V DDEXT = Min) Figure 42. Typical Output Rise/Fall Time (20% to 80%, V DDEXT = Max) LOAD CAPACITANCE (pF) 12 0 50 100 150 200 250 10 8 6 4 R I S E A N D F A L L T I M …

33, ADSP-21367/ADSP-21368/ADSP-21369 Rev. D | Page 33 of 56 | November 2008 Table 30. Serial Ports—Internal Clock Parameter Min Max Unit Timing Requirements t SFSI 1 FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode) 7ns t HFSI 1 FS Hold After SCLK (External…