ON Semiconductor RSL10 Hardware Reference Manual

491, www.onsemi.com 491 ON Semiconductor 0x400100B8 RF_REG2E (31:24) RSSI_DETECT_ABS_THR_RSSI_DET_ABS _THR (31:24) RSSI_DETECT_ABS_THR_RSSI_DET_ABS_ THR 0X0 Threshold used for absolute RSSI detection (23:16) RSSI_DETECT_DIFF_THR_RSSI_DET_DI FF_THR (23:16) RSSI_DETECT_DIFF_THR_RSSI_DET…

338, RSL10 Hardware Reference www.onsemi.com 338 If the SPI*_CTRL0_MODE_SELECT bit in the SPI*_CTRL0 register is set, the SPI interface operates in auto mode to limit the overhead between SPI transfers. This mode works in conjunction with the SPI interface data registers. These registers are: SPI…

514, ON Semiconductor RSL10 RSL10 Hardware Reference www.onsemi.com 514 A.28 SYSTEM CONTROL BLOCK Address Register Name Register Write Register Read Default Description 0xE000ED00 SCB_CPUID - (31:24) IMPLEMENTER 0X41 Implementer code - (23:20) VARIANT 0X2 Implementation variant - (19:16) ARCHITECTURE 0XF Archite…

312, RSL10 Hardware Reference www.onsemi.com 312 11.1.6.8 ADC_BATMON_COUNT_VAL 11.1.6.9 ADC_BATMON_STATUS 11.2 GENERAL-PURPOSE I/O (GPIO) INTERFACE RSL10 can configure any of the DIO pads as software-controlled general-purpose DIO (GPIO) pads. The function of these GPIO pads is defi…

406, RSL10 Hardware Reference www.onsemi.com 406 These registers are part of the ARM Cortex-M3 processor’s NVIC register block. Table 37 describes the field of the Interrupt Set-Enable registers. Table 38 describes the field of the Interrupt Clear-Enable registers. 14.1.3 Interrupt Set-Pending Regi…

500, RSL10 Hardware Reference www.onsemi.com 500 0xE000E180 NVIC_ICER0 (31) DMIC_OUT_OD_IN (31) DMIC_OUT_OD_IN 0X0 DMIC_OUT_OD_IN interrupt clear enable (30) UART_ERROR (30) UART_ERROR 0X0 UART_ERROR interrupt clear enable (29) UART_TX (29) UART_TX 0X0 UART_TX interrupt clear enable (28) …