Xilinx Virtex UltraScale+ FPGAs Operation & User’s Manual

99, Xilinx Virtex UltraScale+ FPGAs The sampled eye diagram is constructed by plong one sample per symbol located at the CDR sampling point (aer the equalizer). By plong mulple samples, the image looks like the gure above. Sampled eye supports both NRZ and PAM4 modulaon, with the only dierence being that …

137, Table 75: DRP Map of GTM_DUAL Primitive (cont'd) DRP Addres s DRP Bits R/W Attribute Name Attribute Bits Attribute Encoding DRP Encoding 0x099 [15:0] R/W CH0_A_CH_CFG4 [15:0] 0–65535 0–65535 0x09a [15:0] R/W CH0_A_CH_CFG5 [15:0] 0–65535 0–65535 0x09b [15:0] R/W CH0_A…

33, Table 16: Recommended Transmitter Resets for Common Situations (cont'd) Situation Components to be Reset Recommended TX Reset Setting TXRESETMODE TXPMARESETMASK TXPCSRESETMASK 1 After assertion/ deassertion of TXPD Entire TX 2'b00 2’b11 2’b11 TX rate change TX PMA and …

121, • Output voltage swing • Jier (determinisc, random, peak-to-peak) • Rise and fall mes • Supply voltage and current • Noise specicaon • Duty cycle and duty-cycle tolerance • Frequency stability These characteriscs are selecon criteria when choosing an osc…

29, The following table lists aributes required by GTM transceiver TX inializaon. In general cases, the reset me required by the TX PMA or the TX PCS varies depending on line rate. The factors aecng PMA reset me and PCS reset me are the user-congurable aributes TX_…

24, Figure 11: GTM Transceiver Initialization Overview After Configuration LCPLL Reset TX Initialization by GTTXRESET RX Initialization by GTRXRESET RXRESETDONETXRESETDONE X20903-052818 The GTM transceiver TX and RX use a state machine to control the inializaon process. They are paro…