Cypress Semiconductor HOTLink II CYV15G0104TRB Manual, Specification Sheet

6, CYV15G0104TRB Document #: 38-02100 Rev. *B Page 6 of 27 Pin Definitions CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDB[9:0] LVTTL Input, synchronous, sampled by TXCLKB↑ or …

24, CYV15G0104TRB Document #: 38-02100 Rev. *B Page 24 of 27 Table 7. Package Coordinate Signal Allocation Ball ID Signal Name Signal Type Ball ID Signal Name Signal Type Ball ID Signal Name Signal Type A01 NC NO CONNECT C07 NC NO CONNECT F17 VCC POWER A02 NC NO CONNECT C08 GND GROUND …

21, CYV15G0104TRB Document #: 38-02100 Rev. *B Page 21 of 27 CYV15G0104TRB Receive PLL Characteristics Over the Operating Range t RXLOCK Receive PLL lock to input data stream (cold start) 376k UI Receive PLL lock to input data stream 376k UI t RXUNLOCK Receive PLL Unlock Rate 46 UI Capac…

15, CYV15G0104TRB Document #: 38-02100 Rev. *B Page 15 of 27 Device Configuration Strategy The following is a series of ordered events needed to load the configuration latches on a per channel basis: 1. Pulse RESET Low after device power-up. This operation resets both channels. 2. Set the static la…

22, Cypress Semiconductor HOTLink II CYV15G0104TRB CYV15G0104TRB Document #: 38-02100 Rev. *B Page 22 of 27 CYV15G0104TRB HOTLink II Transmitter Switching Waveforms (continued) TXCLKOB t TXCLKO Transmit Interface TXCLKOB Timing TXRATE = 1 (internal) REFCLKB t REFCLK t REFL t REFH Note 28 Note 29 TXCLKOB t TXCLKO Transmit Interface TXC…