Cypress Semiconductor CY7C1223H Manual, Specification Sheet

6, Cypress Semiconductor CY7C1223H CY7C1223H Document #: 38-05674 Rev. *B Page 6 of 16 Interleaved Burst Address Table (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND)…

5, CY7C1223H Document #: 38-05674 Rev. *B Page 5 of 16 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1223H supports secondary cache…

4, CY7C1223H Document #: 38-05674 Rev. *B Page 4 of 16 Pin Descriptions Pin Type Description A0, A 1 , A Input- Synchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sample…

11, CY7C1223H Document #: 38-05674 Rev. *B Page 11 of 16 Switching Waveforms Read Timing [16] Note: 16. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH …

10, CY7C1223H Document #: 38-05674 Rev. *B Page 10 of 16 Switching Characteristics Over the Operating Range [14, 15] Parameter Description 166 MHz 133 MHz UnitMin. Max. Min. Max. t POWER V DD (Typical) to the first Access [10] 11 ms Clock t CYC Clock Cycle Time 6.0 7.5 ns t CH Clock HIGH 2.5 3.0…