Cypress Semiconductor CY7C1231H Manual, Specification Sheet

7, Cypress Semiconductor CY7C1231H CY7C1231H Document #: 001-00207 Rev. *B Page 7 of 12 Capacitance [11] Parameter Description Test Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5pF C CLOCK Clock Input Capacitance 5 pF C I/O I/O Capacitance 5 pF Thermal Resistance [11] …

11, CY7C1231H Document #: 001-00207 Rev. *B Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embo…

4, CY7C1231H Document #: 001-00207 Rev. *B Page 4 of 12 Functional Overview The CY7C1231H is a synchronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising …

5, CY7C1231H Document #: 001-00207 Rev. *B Page 5 of 12 Linear Burst Address Table (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Interleaved Burst Sequence First Address Second Address Third Address…

12, CY7C1231H Document #: 001-00207 Rev. *B Page 12 of 12 Document History Page Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 001-00207 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 347377 See ECN PCI New Data Sheet *A…