Specifications:126/126322-cy7c1266v18.pdf file (09 Sep 2023)
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Cypress Semiconductor CY7C1266V18 Computer Hardware PDF Specification Sheet (Updated: Saturday 9th of September 2023 04:20:45 PM)
Rating: 4.8 (rated by 29 users)
Compatible devices: CY7C1460AV33, CY7C1241V18, CY7C1305BV25, CY14B256K, CY8C23533, SL811HS, CY7C1471V33, CY7C63413C.
Recommended Documentation:
6, Cypress Semiconductor CY7C1266V18 CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 6 of 27 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input/Output- Synchronous Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write operations. Thes…
13, CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 13 of 27 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the…
27, Document Number: 001-06347 Rev. *D Revised March 11, 2008 Page 27 of 27 All product and company names mentioned in this document are the trademarks of their respective holders. CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 © Cypress Semiconductor Corporation, 2006-2008. T…
3, CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 3 of 27 Logic Block Diagram (CY7C1268V18) Logic Block Diagram (CY7C1270V18) CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg. R/W DQ [17:0] Output Logic R…
22, CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 22 of 27 Switching Characteristics Over the Operating Range [21, 22] Cypress Parameter Consortium Parameter Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Min Max Min Max Min Max Min Max t …
8, CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 8 of 27 Functional Overview The CY7C1266V18, CY7C1277V18, CY7C1268V18, and CY7C1270V18 are synchronous pipelined Burst SRAMs equipped with a DDR interface. Accesses for both ports are initiated on …
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