Cypress Semiconductor CY7C1324H Manual, Specification Sheet

6, CY7C1324H Document #: 001-00208 Rev. *B Page 6 of 15 Truth Table for Read/Write [2, 3] Function GW BWE BW B BW A Read H H X X Read H L H H Write Byte (A, DQP A )HLHL Write Byte (B, DQP B )HLLH Write All Bytes H L L L Write All Bytes L X X X [+] Feedback …

4, CY7C1324H Document #: 001-00208 Rev. *B Page 4 of 15 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1324H supports secondary cache in syste…

11, CY7C1324H Document #: 001-00208 Rev. *B Page 11 of 15 Write Cycle Timing [15, 16] Note: 16. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW [A:B] LOW. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES …

15, CY7C1324H Document #: 001-00208 Rev. *B Page 15 of 15 Document History Page Document Title: CY7C1324H 2-Mbit (128K x 18) Flow-Through Sync SRAM Document Number: 001-00208 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 347377 See ECN PCI New Data Sheet *A 428408 S…

13, Cypress Semiconductor CY7C1324H CY7C1324H Document #: 001-00208 Rev. *B Page 13 of 15 ZZ Mode Timing [19, 20] Notes: 19. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 20. DQs are in High-Z when exiting ZZ sleep mode. Timing Diagrams (…