Specifications:126/126341-cy7c1338g.pdf file (20 Sep 2023)
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Cypress Semiconductor CY7C1338G Computer Hardware PDF Specification Sheet (Updated: Wednesday 20th of September 2023 03:05:24 PM)
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Compatible devices: NoBL CY7C1460AV25, CY7C0241AV, NoBL CY7C1355C, NoBL CY7C1371D, Perform CY7C1370D, CY7C1166V18, PSoC Style AN2034, CY7C1350G.
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15, CY7C1338G Document #: 38-05521 Rev. *D Page 15 of 17 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part…
4, Cypress Semiconductor CY7C1338G CY7C1338G Document #: 38-05521 Rev. *D Page 4 of 17 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t C0 ) is 6.5 ns (133-MHz device). The CY7C1338G supports secondary cache in systems util…
3, CY7C1338G Document #: 38-05521 Rev. *D Page 3 of 17 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sample…
16, CY7C1338G Document #: 38-05521 Rev. *D Page 16 of 17 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypre…
14, CY7C1338G Document #: 38-05521 Rev. *D Page 14 of 17 ZZ Mode Timing [21, 22] Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in high-Z when exiting ZZ sleep mode. Timin…
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