Cypress Semiconductor CY7C1346H Manual, Specification Sheet

14, CY7C1346H Document #: 38-05672 Rev. *B Page 14 of 16 ZZ Mode Timing [21, 22] Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Switchi…

8, CY7C1346H Document #: 38-05672 Rev. *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied.........................…

1, 2-Mbit (64K x 36) Pipelined Sync SRAM CY7C1346H Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05672 Rev. *B Revised April 26, 2006 Features • Registered inputs and outputs for pipelined operation • 64K × 36 com…

4, CY7C1346H Document #: 38-05672 Rev. *B Page 4 of 16 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1346H supports secondary cache…

10, Cypress Semiconductor CY7C1346H CY7C1346H Document #: 38-05672 Rev. *B Page 10 of 16 Switching Characteristics Over the Operating Range [11, 12] Parameter Description -166 UnitMin. Max. t POWER V DD (Typical) to the First Access [13] 1 ms Clock t CYC Clock Cycle Time 6.0 ns t CH Clock HIGH 2.5 ns t CL Clock LOW 2.5 ns Output…