Cypress Semiconductor CY7C1380C Manual, Specification Sheet

20, CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 20 of 36 119-Ball BGA Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL ID BIT# BALL ID 1 K4 37 B2 2 H4 38 P4 3M439 N4 4F440 R6 5B441 T5 6A442 T3 7G443 R2 8C644 R3 9A645 P2 10 D6 46 P1 11 D7 47 N2 12 E6 48 L2 13 G6 49 K1 14 H7 50 N1 15 E…

30, Cypress Semiconductor CY7C1380C CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 30 of 36 Read/Write Cycle Timing [21, 23, 24] Note: 23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC . 24. GW is HIGH. Switching Waveforms (continued) t CYC…

14, CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 14 of 36 READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L…

32, CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 32 of 36 Ordering Information Speed (MHz) Ordering Code Package Name Part and Package Type Operating Range 250 CY7C1380C-250AC CY7C1382C-250AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial CY7C1380C-250BGC CY7C1382C-250BGC BG1…

18, CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 18 of 36 3.3V TAP AC Test Conditions Input pulse levels ........ ........................................VSS to 3.3V Input rise and fall times...................... ..............................1ns Input timing reference lev…

35, CY7C1380C CY7C1382C Document #: 38-05237 Rev. *D Page 35 of 36 Package Diagrams (continued) i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the …