Cypress Semiconductor CY7C1392BV18 Manual, Specification Sheet

21, CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev. *D Page 21 of 31 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 575 mA (x9) 575 (x18) 600 (x36) 630 167 MHz (x8) 485 mA (x9) 490 (x18) 500 (x36) 540 I SB1 Automatic P…

24, CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev. *D Page 24 of 31 Output Times t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold after Output C/C Clock Rise (Active t…

26, CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev. *D Page 26 of 31 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offe…

5, Cypress Semiconductor CY7C1392BV18 CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev. *D Page 5 of 31 CY7C1393BV18 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/144M NC/36M R/W BWS 1 K NC/288M LD A NC/72M CQ B NC Q9 D9 A NC K BWS 0 ANCNCQ8 C NC NC D10 V SS AAAV SS NC Q7 D8 D NC D11 Q10 V SS V SS V…

9, CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev. *D Page 9 of 31 DLL These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked af…

18, CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 Document #: 38-05623 Rev. *D Page 18 of 31 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26N 299G 566A 831J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5…