Cypress Semiconductor CY7C144 Manual, Specification Sheet

14, CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 14 of 21 Architecture The CY7C144/5 consists of a an array of 8K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any l…

6, CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 6 of 21 Figure 4. AC Test Loads and Waveforms 3.0V GND 90% 90% 10% ≤ 3ns ≤ 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load1) 5V OUTPUT C= 30 pF V TH = 1.4V OUTPUT C = 30pF (b) Th évenin Equivalent (Load 1) (c) Three-State Delay (Load 3) C…

16, CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 16 of 21 Figure 17. Typical DC and AC Characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 −55 25 125 1.2 1.0 120 80 0 1.0 2.0 3.0 4.0 OUTPUT SOURCE CURRENT (mA) SUPPLY VOLTAGE (V) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE NORMALIZ…

15, Cypress Semiconductor CY7C144 CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 15 of 21 Table 3. Non-Contending Read/Write Inputs Outputs CE R/W OE SEM I/O 0−7/8 Operation H X X H High Z Power-Down H H L L Data Out Read Data in Semaphore X X H X High Z I/O Lines Disabled H X L Data In Write to Semaphore LHL HData Out…

18, CY7C145, CY7C144 Document #: 38-06034 Rev. *D Page 18 of 21 8K x9 Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C145-15AC A80 80-Pin Thin Quad Flat Pack Commercial CY7C145-15AXC A80 80-Pin Pb-Free Thin Quad Flat Pack CY7C145-15JC J81 68-Pin Plastic Le…