Cypress Semiconductor CY8C24123 Manual, Specification Sheet

4, CY8C24123 CY8C24223, CY8C24423 Document Number: 38-12011 Rev. *G Page 4 of 43 Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump…

34, CY8C24123 CY8C24223, CY8C24423 Document Number: 38-12011 Rev. *G Page 34 of 43 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40 °C ≤ T A ≤ 85°C, or 3.0V to…

5, CY8C24123 CY8C24223, CY8C24423 Document Number: 38-12011 Rev. *G Page 5 of 43 Development Tools The Cypress MicroSystems PSoC Designer is a Microsoft ® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE an…

8, CY8C24123 CY8C24223, CY8C24423 Document Number: 38-12011 Rev. *G Page 8 of 43 Pinouts The CY8C24x23 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO. However,…

20, Cypress Semiconductor CY8C24123 CY8C24123 CY8C24223, CY8C24423 Document Number: 38-12011 Rev. *G Page 20 of 43 Table 16. 3.3V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes V OSOA Input Offset Voltage (absolute value) Low Power Input Offset Voltage (absolute value) Mid Power High Power is…

28, CY8C24123 CY8C24223, CY8C24423 Document Number: 38-12011 Rev. *G Page 28 of 43 Figure 12. PLL Lock Timing Diagram Figure 13. PLL Lock for Low Gain Setting Timing Diagram Figure 14. External Crystal Oscillator Startup Timing Diagram Figure 15. 24 MHz Period Jitter (IMO) Timing Dia…