Cypress Semiconductor CY7C1298H Manual, Specification Sheet

13, CY7C1298H Document #: 38-05665 Rev. *B Page 13 of 16 Read/Write Timing [16, 18, 19] Notes: 18. The data bus (Q) remains in High-Z following a WRITE cycle, unless a new read access initiated by ADSP or ADSP. 19. GW is HIGH. Switching Waveforms (continued) t CYC t CL CLK ADSP t ADH t AD…

2, Cypress Semiconductor CY7C1298H CY7C1298H Document #: 38-05665 Rev. *B Page 2 of 16 Functional Block Diagram ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSC BW B BWA CE1 DQB, DQPB BYTE WRITE REGISTER DQA , DQPA BYTE WRITE REGISTER ENABLE REGISTER OE SENSE AMPS MEMORY ARRAY ADSP 2 A [1:0] MODE CE2 CE3 GW …

4, CY7C1298H Document #: 38-05665 Rev. *B Page 4 of 16 Pin Descriptions Pin Type Description A0, A 1 , A Input- Synchronous Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and…

1, 1-Mbit (64K x 18) Pipelined DCD Sync SRAM CY7C1298H Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05665 Rev. *B Revised July 5, 2006 Features • Registered inputs and outputs for pipelined operation • Optimal for performanc…

8, CY7C1298H Document #: 38-05665 Rev. *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................... –65°C to + 150° Ambient Temperature with Power Applied...........................…

10, CY7C1298H Document #: 38-05665 Rev. *B Page 10 of 16 Switching Characteristics Over the Operating Range [14, 15] Parameter Description 166 MHz 133 MHz UnitMin. Max. Min. Max. t POWER V DD (Typical) to the first Access [10] 11ms Clock t CYC Clock Cycle Time 6.0 7.5 ns t CH Clock HIGH 2.5…