Cypress Semiconductor SL811HS Manual, Specification Sheet

23, SL811HS Document 38-08008 Rev. *D Page 23 of 32 Package Markings (48-Pin TQFP) YYWW = Date code XXXX = Product code X.X = Silicon revision number Part Number YYWW-X.X XXXX …

13, SL811HS Document 38-08008 Rev. *D Page 13 of 32 Endpoint Control Registers Endpoint n Control Register [Address a = (EP# * 10h), b = (EP# * 10h)+8]. Each endpoint set has a Control register defined as follows: Endpoint Base Address [Address a = (EP# * 10h)+1, b = (EP# * 10h)+9]].…

26, SL811HS Document 38-08008 Rev. *D Page 26 of 32 Bus Interface Timing Requirements I/O Write Cycle Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170 ns minimum. nWR A0 D0-D7 DATA twr twahld twdhld twasu twds…

21, Cypress Semiconductor SL811HS SL811HS Document 38-08008 Rev. *D Page 21 of 32 48/28-Pin USB Host Controller Pins Description The SL811HST-AXC is packaged in a 48-pin TQFP. The SL811HS and SL811HS-JCT packages are 28-pin PLCC’s. These devices require a 3.3 VDC power source. The 48-Pin TQFP requires an exter…

15, SL811HS Document 38-08008 Rev. *D Page 15 of 32 Control Register 1, Address [05h]. The Control register enables or disables USB transfers and DMA operations with control bits. Table 28. Control Register 1 [Address 05h] 7 6 5 4 3 2 1 0 Reserved STBYD SPSEL J-K1 J-K0 DMA Dir DMA …

10, SL811HS Document 38-08008 Rev. *D Page 10 of 32 Interrupt Status Register, Address [Address = 0Dh]. The Interrupt Status register is a READ/WRITE register providing interrupt status. Interrupts are cleared by writing to this register. To clear a specific interrupt, the register i…