Xilinx SP605 Operation & User’s Manual

61, SP605 Hardware User Guide www.xilinx.com 61 UG526 (v1.1.1) February 1, 2010 Appendix C SP605 Master UCF The UCF template is provided for designs that target the SP605. Net names provided in the constraints below correlate with net names on the SP605 rev. C schematic. On identifying the a…

23, SP605 Hardware User Guide www.xilinx.com 23 UG526 (v1.1.1) February 1, 2010 Detailed Description FMC bypass jumper J19 must be connected between pins 1-2 (bypass) to enable JTAG access to the FPGA on the basic SP605 board (without FMC expansion modules installed), as shown in Fi…

49, SP605 Hardware User Guide www.xilinx.com 49 UG526 (v1.1.1) February 1, 2010 Detailed Description Mode DIP Switch SW1 (Active-High) DIP switch SW1 sets the FPGA mode as shown in Figure 1-24 and Table 1-30, page 55. References For more information, refer to the Spartan-6 FPGA Configuration…

54, 54 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board Voltage and current monitoring and control are available for selected power rails through Texas Instruments' Fusion Digital Power™ graphical user interface (GUI). Both onboard TI…

52, 52 www.xilinx.com SP605 Hardware User Guide UG526 (v1.1.1) February 1, 2010 Chapter 1: SP605 Evaluation Board Power Management AC Adapter and 12V Input Power Jack/Switch The SP605 is powered from a 12V source that is connected through a 6-pin (2X3) right angle Mini-Fit type connector J18. The A…

63, Xilinx SP605 SP605 Hardware User Guide www.xilinx.com 63 UG526 (v1.1.1) February 1, 2010 NET "FPGA_CMP_CS_B" LOC = "V18"; ## 4 on J3 NET "FPGA_CMP_MOSI" LOC = "W18"; ## 2 on J3 ## NET "FPGA_D0_DIN_MISO_MISO1" …