Xilinx Virtex-5 FPGA ML561 Operation & User’s Manual

101, Virtex-5 FPGA ML561 User Guide www.xilinx.com 101 UG199 (v1.2.1) June 15, 2009 FPGA #2 Pinout R DDR2 DIMM Deep Interface (cont.) DDR2_DIMM3_CK2_P AA25 DDR2_DIMM_DQ_BY0_B4 R27 DDR2_DIMM3_CKE0 AE28 DDR2_DIMM_DQ_BY0_B5 R26 DDR2_DIMM3_CKE1 AH28 DDR2_DIMM_DQ_BY0_B6 U28 DDR2_DIMM3_CS0_N W25 DDR2_DIMM_DQ_…

7, Virtex-5 FPGA ML561 User Guide www.xilinx.com 7 UG199 (v1.2.1) June 15, 2009 R Preface About This Guide This user guide describes the Virtex ® -5 FPGA ML561 Memory Interfaces Development Board. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx web…

31, Xilinx Virtex-5 FPGA ML561 Virtex-5 FPGA ML561 User Guide www.xilinx.com 31 UG199 (v1.2.1) June 15, 2009 External Interfaces R Power On or Off Slide Switch The power on or off slide switch is a DPST slide switch used to apply input power to the board. While the board contains two such switches, the 5V switch is primar…

28, 28 www.xilinx.com Virtex-5 FPGA ML561 User Guide UG199 (v1.2.1) June 15, 2009 Chapter 3: Hardware Description R 200 MHz LVPECL Clock The 200 MHz LVPECL clock source is an Epson EG-2121CA200M-PCHS oscillator (Y1) with a differential output. The oscillator runs at 200 MHz ± 100 PPM with an operati…

85, Virtex-5 FPGA ML561 User Guide www.xilinx.com 85 UG199 (v1.2.1) June 15, 2009 Signal Integrity Correlation Results R Figure 7-46: QDRII Write Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner) 800.0 1200.0 1600.0 2000.0 2400.0 2800.0 -1900.0 -1400.0 -900.0 -400.0 100.0 600.0 1100.0 1600.0 …

2, Virtex-5 FPGA ML561 User Guide www.xilinx.com UG199 (v1.2.1) June 15, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You ma…