Xilinx PCI32 Manual, Specifications

1, Xilinx PCI32 DS206 August 31, 2005 www.xilinx.com 1 Product Specification v3.0.151 © 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. X…

9, PCI32 Interface v3.0 DS206 August 31, 2005 www.xilinx.com 9 Product Specification v3.0.151 Table 4: Timing Parameters, 66 MHz Implementations Symbol Parameter Min Max T cyc CLK Cycle Time 15 1 30 T high CLK High Time 6 - T low CLK Low Time 6 - T val CLK to Signal Valid Delay (bussed signals…

8, PCI32 Interface v3.0 8 www.xilinx.com DS206 August 31, 2005 Product Specification v3.0.151 Timing Specifications The maximum speed at which your user design is capable of running can be affected by the size and quality of the design. The following tables show the key timing parameters for th…

3, PCI32 Interface v3.0 DS206 August 31, 2005 www.xilinx.com 3 Product Specification v3.0.151 Notes 1. Spartan-3 and Spartan-3E solution pending production speed files. 2. For additional Part/Package combinations, see the UCF Generator in the PCI Lounge. 3. XC2V1000 is supported over Military Temp. ra…

6, PCI32 Interface v3.0 6 www.xilinx.com DS206 August 31, 2005 Product Specification v3.0.151 Target State Machine This block controls the PCI interface target functions. The states implemented are a subset of those defined in Appendix B of the PCI Local Bus Specification. The target control l…

7, PCI32 Interface v3.0 DS206 August 31, 2005 www.xilinx.com 7 Product Specification v3.0.151 Bandwidth The PCI Interface supports fully compliant zero wait-state burst operations for both sourcing and receiving data. This interface supports a sustained bandwidth of up to 264 MBytes/sec. The desi…