Digital Equipment Corporation AlphaPC64 Operation & User’s Manual

69, B.3 Ordering Associated Literature Title Order Number Associated DECchip Documentation DECchip 21071 and DECchip 21072 Core Logic Chipsets Product Brief EC–QH0QA–TE DECchip 21071 and DECchip 21072 Core Logic Chipsets Data Sheet EC–QAEMA–TE Designing a Memory/Cache Subsystem for the DECc…

13, 1.2 System Components and Features Table 1–1 L2 Cache SIMM Sizes L2 Cache Size Static RAM Access Times 512KB 6 ns, 8 ns, 10 ns, 12 ns, 15 ns 2MB 6 ns, 8 ns, 10 ns, 12 ns, 15 ns 8MB 6 ns, 8 ns, 10 ns, 12 ns, 15 ns 1.2.5 Clock Subsystem Overview The clock subsystem provides clocks to the…

11, 1.2 System Components and Features Figure 1–2 Maximum and Minimum SIMM Bank Layouts LJ04134A.AI DRAM 3 Unpopulated J4 DRAM 1 Unpopulated J6 DRAM 2 Unpopulated J5 DRAM 0 Unpopulated J7 DRAM 3 - 4MB SIMM memData96 - 127 + Parity J8 DRAM 1 - 4MB SIMM memData32 - 63 + Parity J10 DRAM…

57, Digital Equipment Corporation AlphaPC64 4.4 Flash ROM (System ROM) Changing TOY RAM Location 3F—Debug Monitor bootopt Command Use the debug monitor bootopt command to change the value in location 3F. In the example shown here, the bootopt command is used to change the value in location 3F from 0 to 1: AlphaPC64> bootopt 1 …

76, S Saturn IO chip See SIO chip Serial interface, 1–5 Serial ROM See SROM, code; SROM, test connector SIMM bank layouts, 1–1 DRAM, 1–1 SRAM, 1–4 Single inline memory module See SIMM SIO chip, 1–5, 4–1 interrupt logic, 4–1 Software configuration jumpers, 2–1, 2–3, …