Specifications:231/231660-tms320dm36x.pdf file (27 Dec 2023)
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Texas Instruments TMS320DM36X Media Converter, Network Card PDF Operation & User’s Manual (Updated: Wednesday 27th of December 2023 09:29:36 AM)
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Compatible devices: ThunderLAN TNETE211, LM5180-Q1, THS1031, DAC7741EVM, TMS320C6452 DSP, TLV320AIC3107EVM-K, TMS320TCI648x, ADS868 Series.
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117, www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 78 and described in Table 76. Figure 78. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNU…
128, Ethernet Media Access Controller (EMAC) Registers www.ti.com CRC errors have no effect on this statistic. 5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL) The total number of frames when transmission was abandoned due to excessive collisions. Such a frame is define…
29, www.ti.com Architecture 2.6.5.11 Pass CRC (PASSCRC) Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-byte CRC. This flag should be cleared by the software application before submitting the descriptor to the receive queue. 2.6.5.12 Jabber Flag This …
52, Architecture www.ti.com Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* Disable all the EMAC/MDIO interrupts in the control module */ EmacControlRegs->CONTROL.C_RX_EN = 0; EmacControlRegs->CONTROL.C_TX_EN = 0; EmacControlRegs->CONTROL.C_RX_THRESH_EN = 0;…
17, Texas Instruments TMS320DM36X www.ti.com Architecture Table 1. EMAC and MDIO Signals for MII Interface Signal Type Description EMAC_TX_CLK I Transmit clock (EMAC_TX_CLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The EMAC_TXD and EMAC_TX_EN signals are ti…
91, www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 47 and described in Table 45. Figure 47. Transmit Interrupt Status (Mask…
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