Texas Instruments TAS3002 Data Manual

Data Manual for Texas Instruments TAS3002 Processor (57 pages)

Specifications:

231/231846-tas3002.pdf file (26 Jan 2024)
  • Manufacturer: Texas Instruments
  • Category of Device: Processor
  • Document: TAS3002, File Type: PDF Data Manual
  • Updated: 26-01-2024
  • Count of Pages: 57
Download TAS3002 Manual (57 pages)

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Data: UPD 26th January 2024

Texas Instruments TAS3002 Processor PDF Data Manual (Updated: Friday 26th of January 2024 01:49:15 AM)

Rating: 4.4 (rated by 42 users)

Compatible devices: TMS320VC5509, OMAP5910, Sitara AM335x, Sitara AM3352, DM38x DaVinci, SM320F2812-HT Data, TMS320C28x, TMS320C2x.

Recommended Documentation:

Text Version of Texas Instruments TAS3002 Processor Manual (Summary of Contents)

(Ocr-Read of Texas Instruments TAS3002 Document (Main Content), UPD: 26 January 2024)
  • 46, 8−3 0.002 −0.002 Amplitude − dB 0.004 0.006 0.008 0 0 f − Frequency − Hz 0.1 f s 0.2 f s 0.3 f s 0.4 f s 0.5 f s Figure 8−3. ADC Digital Filter Pass-Band Characteristics −0.4 −1 Amplitude − dB −0.2 0 0.2 −0.6 −0.8 0 f − Frequency − Hz 1 f s 2 f s 3 f s 4 f s Figure…

  • 55, TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TAS3002PFBR TQFP PFB 48 0 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION…

  • 4, 1−3 Control PWR_DN TEST AINRP AINRM AINLM AINLP 24-Bit Stereo ADC RINA RINB AINRM AINRP AINLM AINLP LINA LINB Control CS1 SDA SCL Controller GPI0 GPI1 GPI2 GPI3 GPI4 GPI5 24-Bit Stereo DAC CAP_PLL MCLK XTALO MCLKO CLKSEL SDIN2 SDIN1 SDATA Control LRCLK/O SCLK/O SDOUT1 L L+R SDOUT2 32-Bit Audio …

  • 52, Texas Instruments TAS3002 10−1 10 Mechanical Information The TAS3002 device is packaged in a 48-terminal PFB package. The following illustration shows the mechanical dimensions for the PFB package. PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN…

  • 12, 2−5 2.3 Switching Characteristics PARAMETER MIN TYP MAX UNIT t c(SCLK) SCLK cycle time 325.5 ns t d(SLR) SCLK rising to LRCLK edge 20 ns t d(SDOUT) SDOUT valid from SCLK falling edge (see Note 1) (1/256f S ) + 10 ns t su(SDIN) SDIN setup before SCLK rising edge 20 ns t h(SDIN) SDIN hold aft…

DOC-2025aba4:

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