Siemens ERTEC200 Manual 

Manual  for Siemens ERTEC200 Switch (97 pages)

Specifications:

328/328127-ertec200.pdf file (05 Mar 2024)
  • Manufacturer: Siemens
  • Category of Device: Switch
  • Document: ERTEC200, File Type: PDF Manual 
  • Updated: 05-03-2024
  • Count of Pages: 97
Download ERTEC200 Manual (97 pages)

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Data: UPD 5th March 2024

Siemens ERTEC200 Switch PDF Manual  (Updated: Tuesday 5th of March 2024 09:55:18 PM)

Rating: 4.6 (rated by 14 users)

Compatible devices: RUGGEDCOM RSG920P, SIMATIC NET RUGGEDCOM RS8000A, 3NP19 0-1FA00 Series, Pointek CLS300, SIRIUS 3SE5250 Series, 3WN Series, SIMATIC NET RUGGEDCOM RS910L, HiPath 1120.

Recommended Documentation:

Text Version of Siemens ERTEC200 Switch Manual (Summary of Contents)

(Ocr-Read of Siemens ERTEC200 Document (Main Content), UPD: 05 March 2024)
  • 71, SDRAM Bank Config W/R Addr.: 0x7000_0008 Default: 0x0000_20A0 Description SDRAM bank config register Bit No. Name Description 31..14 Reserved Reserved 13* CL CAS latency 0: SDRAM is activated with CAS latency = 2 1: SDRAM is activated with CAS latency = 3 12..1…

  • 52, UARTCR R/W Addr.: 0x4000_2314 Default: 0x00 Description UART control registers Bit No. Name Description 0 UARTEN UART Enable = 1 UART sending/receiving of data is enabled 1 SIREN SIR enable = 1 IrDA SIR Endec is enabled. The bit can only be ch…

  • 62, ARM9_CTRL R/W Addr.: 0x4000_2650 Default: 0x0000_1939 Description Check of ARM9 inputs that are not accessible from external pins. This register can only be written to if the Write enable bit is set in the ARM9_WE register. This register can only be changed for debugging purpo…

  • 5, Siemens ERTEC200 Contents 1 Introduction ............................................................................................................................9 1.1 Applications of the ERTEC 200..............................................................................................…

  • 66, f/MHz t/µs t LOCK = 645 µs 35 Power-up PLL a c t i v e R e s e t 300 Figure 11: Power-Up Phase of the PLL The lock status of the PLL is monitored by the hardware. Loss of the input clock and PLL not locked status is signaled with interrupt FIQ3. The state of the PLL can also be…

  • 38, GPIO2_ IN R Addr.: 0x4000_2528 Default: Port assignment Description Input register for General Purpose IO [44:32] Bit No. Name Description 31..13 Reserved Reserved 12..0 GPIO2_IN[44:32] 0: GPIO inputx = 0, 1: GPIO inputx = 1 4.3 Timer 0/1/2 T…

DOC-e0c8b6d4:

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