Renesas M65881AFP Manual, Specification Sheet

3, Rev.1.00 2003.05.08 page 3 of 23 M65881AFP BLOCK DIAGRAM M C K S E L F s o C K O F s o I X f s o O U T X f s o I N S F L A G OUTR1 OUTL1 OUTR2 OUTL2 Sampling Rate Converter Gain Control DATA BCK LRCK S C D T S C S H I F T S C L A T C H 18 17 16 2 41 39 4 I N I T N S P M U T E X f s i I N Clock…

15, Rev.1.00 2003.05.08 page 15 of 23 M65881AFP • Soft Mute The Soft Mute function is executed by setting of Gain Data as 00000/00000000b (" / " means dividing point between index part and mantissa part). The release from Soft Mute Function must be executed by setting the gain data befo…

9, Rev.1.00 2003.05.08 page 9 of 23 M65881AFP FsoCKO is clock output pin of 1fso frequency. The output is divided-clock of XfsoIN, and frequency is free-running at power on. FsoCKO pin's clock is utilized for a synchronization in case that have used plural M65881AFP, take a synchronizat…

13, Rev.1.00 2003.05.08 page 13 of 23 M65881AFP SERIAL CONTROL bit Flag name Functional Explanation H L INIT 1 MODE1 Mode setting1 "L" fixed – 2 MODE2 Mode setting2 "L" fixed – 3 TEST1 Test Mode 1 "L" fixed L 4 TEST2 Test Mode 2 "L" fixed L 5 …

11, Renesas M65881AFP Rev.1.00 2003.05.08 page 11 of 23 M65881AFP HPOUTL1, HPOUTL2, HPOUTR1 and HPOUTR2 are output pins for Headphone output. PWM output modulated ∆Σ output data to pulse width. The Phase of PWM Output for Power Stage and PWM Output for Headphone. The output for Headphone is reverse…

2, Rev.1.00 2003.05.08 page 2 of 23 M65881AFP PIN CONFIGURATION VddL VssRVssL OUTL2 XOVdd XfsoOUT XOVss DVdd DVss MCKSEL SCDT SCSHIFT SCLATCH NSPMUTE INIT LRCK BCK DATA BFVdd SFLAG TEST2 TEST1 HPOUTR2 HPVssR HPOUTR1 HPVddR HPOUTL2 HPVssL HPOUTL1 HPVddL XVss XfsoIN XVdd VssLR OUTR2 OUTR1 VddR 1.8V…