Intel 386 Operation & User’s Manual

Operation & User’s Manual for Intel 386 Computer Hardware (691 pages)

Specifications:

473/473244-386.pdf file (23 Jan 2024)
  • Manufacturer: Intel
  • Category of Device: Computer Hardware
  • Document: 386, File Type: PDF Operation & User’s Manual
  • Updated: 23-01-2024
  • Count of Pages: 691
Download 386 Manual (691 pages)

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Data: UPD 23rd January 2024

Intel 386 Computer Hardware PDF Operation & User’s Manual (Updated: Tuesday 23rd of January 2024 06:17:59 AM)

Rating: 4.2 (rated by 98 users)

Compatible devices: I/O Processor, Centrino Pro, NetBurst, Xeon Phi, MultiProcessor, 945G - Bulk Single Unit Atx Exp, SC5650SCWS, KEMX-2030.

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Text Version of Intel 386 Computer Hardware Manual (Summary of Contents)

(Ocr-Read of Intel 386 Document (Main Content), UPD: 23 January 2024)

  • 516, 18-3 JTAG TEST-LOGIC UNIT 18.2 TEST-LOGIC UNIT OPERATION 18.2.1 Test Access Port (TAP) The test access port consists of five dedicated pins (four inputs and one output). It is through these pins that all communication with the test-logic unit takes place. This unit has its own clock…

  • 330, Intel 386 11-43 ASYNCHRONOUS SERIAL I/O UNIT /***************************************************************************** Service_RBF: Description: Service routine for interrupts generated by RBF signal. This routine is used for…

  • 411, Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL 13-12 13.2.2.2 Autotransmit Mode Set the AUTOTXM bit (SSIOCON2.2) and the TXMM bit (SSIOCON2.1) to enable Autotrans- mit mode. When the AUTOTXM bit is set, the word is automatically transferred to the shift reg- ister and the THBE bit is set. …

  • 596, D-31 SYSTEM REGISTER QUICK REFERENCE D.28 IDCODE Identification Code Register IDCODE Reset State: 2027 0013H (3V) 2827 0013H (5V) 31 24 00100 (3V) 1 (5V) 000 23 16 0010 0111 15 8 0000 0000 7 0 0001 0011 Bit Number Bit Mnemonic Function 31–28 V3:0 Device version number. 27–12 PN15:0 Dev…

  • 486, 16-7 INPUT/OUTPUT PORTS 16.2.1 Pin Configuration You select the operating mode of each pin by writing to the associated bit in the PnCFG registers (Figure 16-3 gives an abbreviated version of these registers; for the complete register descrip- tions, see Appendix D). Setting a bit sele…

DOC-149abb9:

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