Intel P8700 - Core 2 Duo Processor Manual, Datasheet

Manual, Datasheet for Intel P8700 - Core 2 Duo Processor Processor (113 pages)

Specifications:

474/474351-p8700__core_2_duo_processor.pdf file (23 Feb 2024)
  • Manufacturer: Intel
  • Category of Device: Processor
  • Document: P8700 - Core 2 Duo Processor, File Type: PDF Datasheet
  • Updated: 23-02-2024
  • Count of Pages: 113
Download P8700 - Core 2 Duo Processor Manual (113 pages)

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Data: UPD 23rd February 2024

Intel P8700 - Core 2 Duo Processor Processor PDF Datasheet (Updated: Friday 23rd of February 2024 10:04:15 AM)

Rating: 4.8 (rated by 27 users)

Compatible devices: E6700 - Core 2 Duo Dual-Core Processor, HH80552PG0962M - Pentium 4 3.4 GHz Processor, BX80571E7400 - Core 2 Duo 2.8 GHz Processor, 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011, 630 - Pentium 4 630 3.0GHz 800MHz 2MB Socket 775 CPU, Pentium 4, CELERON PROCESSOR P4505 - ADDENDUM, EP80579.

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Text Version of Intel P8700 - Core 2 Duo Processor Processor Manual (Summary of Contents)

(Ocr-Read of Intel P8700 - Core 2 Duo Processor Document (Main Content), UPD: 23 February 2024)

  • 30, Electrical Specifications 30 Datasheet 3.7 FSB Signal Groups The FSB signals have been combined into groups by buffer type in the following sections. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly…

  • 39, Intel P8700 - Core 2 Duo Processor Datasheet 39 Electrical Specifications NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the sa…

  • 37, Datasheet 37 Electrical Specifications NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the…

  • 54, Package Mechanical Specifications and Pin Information 54 Datasheet Figure 11. 3-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) B6740-01 D76564(2) TOP VIEW SIDE VIEW BOTTOM VIEW CORNER KEEP OUT ZONE 4X EDGE KEEP OUT ZONE 4X 4X 7.00 4X 5.00 4X 7.00 13.97 6.985 13.97 6.985 1.6…

  • 27, Datasheet 27 Electrical Specifications 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 …

  • 95, Datasheet 95 Package Mechanical Specifications and Pin Information DEFER# Input DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal mus…

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