Omega Engineering PCI-DAS1001 Operation & User’s Manual

Operation & User’s Manual for Omega Engineering PCI-DAS1001 Network Card (39 pages)

Specifications:

592/592933-pcidas1001.pdf file (07 Oct 2023)
  • Manufacturer: Omega Engineering
  • Category of Device: Network Card
  • Document: PCI-DAS1001, File Type: PDF Operation & User’s Manual
  • Updated: 07-10-2023
  • Count of Pages: 39
Download PCI-DAS1001 Manual (39 pages)

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Data: UPD 7th October 2023

Omega Engineering PCI-DAS1001 Network Card PDF Operation & User’s Manual (Updated: Saturday 7th of October 2023 06:22:54 PM)

Rating: 4.3 (rated by 18 users)

Compatible devices: IOP-241, OMB-DBK-34A, iLD46-EI Series, OMG-COMM232-PCI, DAQ-12, Wireless Sensor System zSeries, WB-31, OM-SQ2020 Series.

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Text Version of Omega Engineering PCI-DAS1001 Network Card Manual (Summary of Contents)

(Ocr-Read of Omega Engineering PCI-DAS1001 Document (Main Content), UPD: 07 October 2023)

  • 21, INT[1:0] General Interrupt Source selection bits. AD FIFO Not Empty11 AD FIFO Half Full01 End of Channel Scan10 Not Defined 00 SourceINT0 INT1 INTE Enables interrupt source selected via the INT[1:0] bits. 1 = Selected interrupt Enabled 0 = Selected interrupt Disabled EOAIE Enables En…

  • 33, 8254B CONTROL REGISTER BADR3 + Bh WRITE ONLY D0D1D2D3D4D5D6D7 01324567 The control register is used to set the operating Modes of 8254B Counters 0,1 & 2. A counter is configured by writing the correct Mode information to the Control Register, then the proper count data must be written to the …

  • 36, Omega Engineering PCI-DAS1001 8.2 ANALOG OUTPUT D/A type AD7847AR Resolution 12 bits Number of channels 2 Output Ranges ±10V, ±5V, 0-5V, 0-10V. Each channel independently programmable. D/A pacing Software Data transfer Programmed I/O. Offset error ±600µV max, all ranges (calibrated) Gain error ±0.02% FSR…

  • 28, 7.4 BADR2 The I/O Region defined by BADR2 contains the ADC Data register and the ADC FIFO clear register. 7.4.1 ADC DATA REGISTER BADR2 + 0 ADC Data register. WRITE Writing to this register is only valid for SW initiated conversions. The ADC Pacer source must be set to 00 via the ADPS[1:0] bi…

  • 23, The following tables summarizes all possible Offset/Range configurations : PCI-DAS1002 305 uV8 0-1.25V 111 610 uV4 0-2.5V 011 1.22 mV2 0-5V 101 2.44 mV1 0-10V 001 610 uV8 ±1.25V 110 1.22 mV4 ±2.5V 010 2.44 mV2 ± 5V 100 4.88 mV1 ±10V 000 Measurement Resolution Input GainInput…

  • 27, 7.3.5 DAC CONTROL/STATUS REGISTER BADR1 + 8 This register selects the DAC gain/range and update modes. This is a Write-only register. WRITE - DACEN-----MODEDAC0R0DAC0R1DAC1R0DAC1R1---- 0123456789101112131415 DACEN This bit enables the Analog Out features of the board. 1 = DAC0/1 en…

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