Supermicro P8SGA Operation & User’s Manual

60, P8SGA User's Manual 4-10 Onboard Parallel Port This setting allows the user to set the address and the corresponding IRQ for the onboard parallel port. The options are Disabled, 378/IRQ7, 278/IRQ5 and 3BC/IRQ7. Parallel Port Mode This setting sets the mode for the onboard Parallel po…

31, Chapter 2: Installation 2-13 Chassis Intrusion The Chassis Intrusion header is lo- cated at JL1. See the board layout in Chapter 1 for the location of JL1 and the table on the right for pin defi nitions. Pin Number 1 2 Definition Intrusion Input Ground Chassis Intrusion Pin Definit…

28, 2-10 P8SGA User's Manual B A A. IDE LED B. PWR LED Pin# 1 3 5 7 Definition IDE LED Active IDE LED Active IDE LED+ IDE LED+ IDE LED+ Pin 1:IDE LED+ Pin 3: IDE LED Active Pin 5: IDE LED Active Pin 7: IDE LED+ Pin 9: Power LED+ Pin 11: X Pin 13: Power LED- Pin 15: Keylock Pin …

57, Chapter 4: BIOS 4-7 PWRON After PWR-Fail This setting allows the user to specify how the system will respond after power loss. The options are Off, On and Former-Sts. Watch Dog Timer Select This setting is for enabling the Watch Dog feature. The options are Disabled, 10 Sec, 20 Sec, 30 Sec…

18, 1-12 P8SGA User’s Manual It also provides two high-speed, 16550 compatible serial communication ports (UARTs). Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability and a processor interrupt sys- tem. Both UARTs provide legacy spe…

47, Supermicro P8SGA 3-3 Chapter 3: Troubleshooting 3. If you still cannot resolve the problem, include the following information when contacting Super Micro for technical support: • Motherboard model and PCB revision number • BIOS release date/version (this can be seen on the initial display wh…