Altera UG-01080 Operation & User’s Manual

116, 1G/10GbE PHY Interfaces Figure 5-2: 1G/10GbE PHY Top-Level Signals xgmii_tx_dc[71:0] xgmii_tx_clk xgmii_rx_dc[71:0] xgmii_rx_clk gmii_tx_d[7:0] gmii_rx_d[7:0] gmii_tx_en gmii_tx_err gmii_rx_err gmii_rx_dv led_char_err led_link led_disp_err led_an mgmt_clk mgmt_clk_reset mgmt_addre…

611, XCVR_ANALOG_SETTINGS_PROTOCOL assigns a value to XCVR_RX_BYPASS_EQ_STAGES_234. If you also assign a value to this parameter, a Quartus II Fitter error results as shown in the following example: Example 19-2: Error (21215) Error resolving parameter "pm_rx_sd_bypass_eqz_stages_234" val…

540, The register-based write to turn on continuous adaptive DFE for logical channel 0 is as shown in the following example: Example 16-1: Register-Based Write To Turn On Adaptive DFE for Logical Channel 0 #Setting logical channel 0 write_32 0x18 0x0 #Setting DFE offset to 0x0 write_32 0x1B …

660, Altera UG-01080 ALTGX (23) Custom PHY Width rx_freqlocked rx_is_lockedtodata [<n>-1:0] Transceiver Control and Status Signals gxb_powerdown phy_mgmt_clk_reset — rx_dataoutfull — — tx_dataoutfull — — rx_pll_locked There are both pll_locked and rx_pll_clocked in Stratix IV. Stratix…

76, Related Information Component Interface Tcl Reference 10GBASE-KR PHY Clock and Reset Interfaces This topic provides a block diagram of the 10GBASE-KR clock and reset connectivity and describes the clock and reset signals. Use the Transceiver PHY Reset Controller IP Core to automatically contro…

455, Offset Bits R/W Name Description 0x135 [15:12] R/W Square Wave Pattern Specifies the number of consecutive 1s and 0s. The following values are available: 1, 4, 5, 6, 8, and 10. [10] R/W TX PRBS 7 Enable Enables the PRBS-7 polynomial in the transmitter. [8] R/W TX PRBS 23 Enable Enables th…