AMD Athlon Processor x86 Optimization Manual

158, 142 Fetch and Decode Pipeline Stages AMD Athlon™ Processor x86 Code Optimization 22007E/0—November 1999 Figure 5. Fetch/Scan/Align/Decode Pipeline Hardware The most common x86 instructions flow through the DirectPath pipeline stages and are decoded by hardware. The less common instructi…

89, Use MOVZX and MOVSX 73 22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization Example 1 (Avoid): ADD EBX, ECX ;inst 1 MOV EAX, DWORD PTR [10h] ;inst 2 (fast address calc.) MOV ECX, DWORD PTR [EAX+EBX] ;inst 3 (slow address calc.) MOV EDX, DWORD PTR [24h…

255, Index 239 22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization T TBYTE Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Trigonometric Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 103 V VectorPath Decoder . . . . . . …

10, x Contents AMD Athlon™ Processor x86 Code Optimization 22007E/0—November 1999 PerfCtr[3:0] MSRs (MSR Addresses C001_0004h–C001_0007h) . . . . . . . . . . . . . 167 Starting and Stopping the Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . .…

238, AMD Athlon Processor x86 222 DirectPath Instructions AMD Athlon™ Processor x86 Code Optimization 22007E/0—November 1999 JNO short disp8 JB/JNAE short disp8 JNB/JAE short disp8 JZ/JE short disp8 JNZ/JNE short disp8 JBE/JNA short disp8 JNBE/JA short disp8 JS short disp8 JNS short disp8 JP/JPE short dis…

187, 22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization Introduction 171 Appendix E Programming the MTRR and PAT Introduction The AMD Athlon™ processor includes a set of memory type and range registers (MTRRs) to control cacheability and access to specified memory regions. The p…