ON Semiconductor KAI-2093 Operation & User’s Manual

Operation & User’s Manual for ON Semiconductor KAI-2093 Motherboard (25 pages)

Specifications:

822/822178-kai2093.pdf file (28 Jul 2023)
  • Manufacturer: ON Semiconductor
  • Category of Device: Motherboard
  • Document: KAI-2093, File Type: PDF Operation & User’s Manual
  • Updated: 28-07-2023
  • Count of Pages: 25
Download KAI-2093 Manual (25 pages)

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Data: UPD 28th July 2023

ON Semiconductor KAI-2093 Motherboard PDF Operation & User’s Manual (Updated: Friday 28th of July 2023 06:38:40 PM)

Rating: 4.4 (rated by 20 users)

Compatible devices: AR0832EASC25SUFAH-GEVB, NCD9830GEVB, CAT4101, NCP1083QBCGEVB, CAT4106, MT9M021IA3XTMZH-GEVB, AR0832EA, A5191HRTNGEVB.

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Text Version of ON Semiconductor KAI-2093 Motherboard Manual (Summary of Contents)

(Ocr-Read of the ON Semiconductor KAI-2093 Document (Main Content), UPD: 28 July 2023)
  • 2, EVBUM2277/D http://onsemi.com 2 Figure 1. Serial Input Timing SLOAD_INPUT SDATA_INPUT SCLK_INPUT DS2 DS1 DS0 R/W A0 A1 A2 A3 (or Test) D0 D1 D2 D3 D4 Dn … (decoded PLD output) SLOAD_xxx The first 3 bits in the datastream are the Device Select bits DS[2..0], sent MSB first, as shown in Figure 1. The Device Sele…

  • 25, ON Semiconductor KAI-2093 EVBUM2277/D http://onsemi.com 25 REFERENCES [1] KAI−2093 Device Specification [2] KAI−2001/KAI−2020/KAI−2093 Imager Board User Manual [3] KAI−2001/KAI−2020/KAI−2093 Imager Board Schematic [4] KSC−1000 Timing Generator Board User Manual [5] KSC−1000 Timing Generator Board Schematic [6] Anal…

  • 19, ON Semiconductor KAI-2093 EVBUM2277/D http://onsemi.com 19 The Altera PLD default KSC−1000 settings contain 2×2 Binning Mode timing in Frame Table 2 (See Figure 11). In order to activate the 2×2 Binning Mode, the Frame Table Pointer (Register 0) must be changed to a value of 2. This is done by setting SW2 HIGH and pressi…

  • 6, EVBUM2277/D http://onsemi.com 6 Table 7. CCD TIMING (continued) Description Notes Pixel Counts TimeSymbol VCCS Pedestal Time T 3P 25.05 ms 501 Photodiode Transfer Time TV 3rd 12.30 ms 246 V2 3 rd Level Photodiode Delay T 3D 20.00 ms 400 Photodiode Frame Delay T 3FD 85.50 ms 1710 Delay before 1 st …

  • 5, ON Semiconductor KAI-2093 EVBUM2277/D http://onsemi.com 5 Outputs The Altera PLD outputs include: the 3-wire serial interface; control signals to the KSC−1000; the INTEGRATE signal used for external monitoring and synchronization; the PLD[2..0] signals which are auxiliary Imager Board control bits; and the GIO[2..0] bits which …

  • 7, ON Semiconductor KAI-2093 EVBUM2277/D http://onsemi.com 7 Table 9. DEFAULT AD9845A AFE REGISTER PROGRAMMING Register Address Description Value (decimal) Notes 0 Operation 128 1 VGA Gain (KAI−2093) 340 Corresponds to a VGA Stage Gain of 9.9 dB 2 Clamp 96 The Output of the AD9845A will be Clamped to Code 96 during the CLPOB Period 3…

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