IDT TSI384 Operation & User’s Manual

Operation & User’s Manual for IDT TSI384 Computer Hardware (281 pages)

Specifications:

807/807919-tsi384.pdf file (06 Apr 2024)
  • Manufacturer: IDT
  • Category of Device: Computer Hardware
  • Document: TSI384, File Type: PDF Operation & User’s Manual
  • Updated: 06-04-2024
  • Count of Pages: 281
Download TSI384 Manual (281 pages)

Read PDF Document Online:

Data: UPD 6th April 2024

IDT TSI384 Computer Hardware PDF Operation & User’s Manual (Updated: Saturday 6th of April 2024 11:02:26 PM)

Rating: 4.8 (rated by 59 users)

Compatible devices: Series 6, i.MX RT1170, USB-BRIDGEV2-EVAL, Digital Encoder Plus, MegaRAID SCSI 320-2X, DBP 7+4, PCISA-3716E2V, rl78/g1g.

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Text Version of IDT TSI384 Computer Hardware Manual (Summary of Contents)

(Ocr-Read of IDT TSI384 Document (Main Content), UPD: 06 April 2024)

  • 171, 14. Register Descriptions 171 Tsi384 User Manual May 5, 2014 Integrated Device Technology www.idt.com 16 S_PERESP Parity Error Response Enable This bit controls the Tsi384’s response to uncorrectable address, attribute, and data errors on the PCI/X Interface. If this bit is set, the bridge must …

  • 220, 14. Register Descriptions220 Tsi384 User Manual May 5, 2014 Integrated Device Technology www.idt.com 14.9.3 PCIe Uncorrectable Error Mask Register Register name: PCIE_UERR_MASK Reset value: 0x0000_0000 Register offset: 0x108 Bits 7 6 5 4 3 2 1 0 31:24 Reserved 23:16 Reserved UR ECRC MAL…

  • 163, 14. Register Descriptions 163 Tsi384 User Manual May 5, 2014 Integrated Device Technology www.idt.com 14.3.9 PCI PFM Base Upper 32 Address Register 14.3.10 PCI PFM Limit Upper 32 Address Register Register name: PCI_PFM_B_UPPER Reset value: 0x0000_0000 Register offset: 0x028 Bits 7 6…

  • 48, IDT TSI384 4. Addressing48 Tsi384 User Manual May 5, 2014 Integrated Device Technology www.idt.com Figure 9: 64-bit Prefetchable Memory Address Range 4.4 I/O Space I/O Base, I/O Limit, I/O Base Upper 16 Bits, and I/O Limit Upper 16 Bits registers in the Tsi384 configuration header specify an addre…

  • 82, 9. Error Handling82 Tsi384 User Manual May 5, 2014 Integrated Device Technology www.idt.com ERR_NONFATAL messages are enabled for transmission if either of the following bits is set: SERR_EN in “PCI Control and Status Register”, or NFTL_ERR_EN in “PCIe Device Control and S…

  • 146, 14. Register Descriptions146 Tsi384 User Manual May 5, 2014 Integrated Device Technology www.idt.com The advanced error reporting capability register is shown below. Table 41: Advanced Error Reporting Capability Registers 31 0 Offset Page PCIe Enhanced Capability Header 0x100 218 Uncorrectabl…

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