ARM ARM966E-S Technical Reference Manual

89, Coprocessor Interface ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 7-9 7.4 Interlocked MCR If the data for a MCR operation is not available inside the ARM9E-S core pipeline during its first Decode cycle, then the ARM9E-S core pipeline interlocks for one o…

169, AC Parameters ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. B-11 The DMA interface timing parameters are shown in Figure B-11 Figure B-11 DMA interface timing CLK DMAReady DMARData DMAENABLE DMAnREQ DMAA DMAMAS DMAD DMAWait T ovdma T ohdma T isdma T ihdma …

21, ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 2-1 Chapter 2 Programmer’s Model This chapter describes the programmer’s model for the ARM966E-S. It contains the following sections: • About the programmer’s model on page 2-2 • About the ARM9E-S programmer’s…

90, Coprocessor Interface 7-10 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A 7.5 CDP CDP instructions normally execute in a single cycle. Like all the previous cycles, nCPMREQ is driven LOW to signal when an instruction is entering the Decode and then the Execute stage of …

82, Coprocessor Interface 7-2 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A 7.1 About the coprocessor interface ARM966E-S fully supports the connection of on-chip coprocessors through the external coprocessor interface and supports all classes of coprocessor instructions. The int…

128, ARM ARM966E-S Test Support 10-6 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A 10.3.3 Pause modes The suggested production test sequence for the SRAM is: 1. Test each SRAM using a full test. 2. Test the BIST hardware for each SRAM. To allow testing of the BIST hardware, a pau…