Renesas H8S/2437 Hardware Manual

602, Rev. 1.00, 09/03, page 564 of 704 (4) Erasing and Programming Procedure in User Program Mode By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 20.13 shows …

105, Rev. 1.00, 09/03, page 67 of 704 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected. IRQ7 to IRQ0 Input Maskab…

140, Rev. 1.00, 09/03, page 102 of 704 6.5 Bus Interface The normal extended bus interface enables direct connection between the ROM and SRAM. For details on the basic area and areas 1 to 3 bus specification selection, refer to tables 6.2 and 6.3. For multiplex extended bus interfac…

426, Renesas H8S/2437 Rev. 1.00, 09/03, page 388 of 704 2fH mask generator Clock Capture FRC CMM IHI signal Internal clock 2fH modification signal Comparator M 1 2 OCRDM ICRD FRT Figure 13.10 Block Diagram for 2fH Modification of IHI Signal Table 13.8 Examples of TCR, TCSR, TCOR, and OCRDM Setting…

326, Rev. 1.00, 09/03, page 288 of 704 11.6.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts the occurrence of compare-match A for the TMR0. The TMR0 and TMR1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupt…

621, Rev. 1.00, 09/03, page 583 of 704 20.8 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the internal SCI. The serial communication interface specification is shown below. (1) Stat…