Xilinx HDMI 1.4 Product Manual

98, HDMI 1.4/2.0 TX Subsystem 98 PG235 October 4, 2017 www.xilinx.com Appendix C: Application Software Development 5. HDCP 1.4 Timer Interrupt (only available when HDCP 1.4 is enabled in hardware) 6. HDCP 2.2 Timer Interrupt (only available when HDCP 2.2 is enabled in hardware) Application Call…

80, Xilinx HDMI 1.4 HDMI 1.4/2.0 TX Subsystem 80 PG235 October 4, 2017 www.xilinx.com Appendix A: Verification, Compliance, and Interoperability 1080p24 2750 1920 1125 1080 24 1080p25 2640 1920 1125 1080 25 1080p30 2200 1920 1125 1080 30 1080p50 2640 1920 1125 1080 50 1080p60 2200 1920 1125 1080 60 1…

90, HDMI 1.4/2.0 TX Subsystem 90 PG235 October 4, 2017 www.xilinx.com Appendix C: Application Software Development Usage The HDMI 1.4/2.0 Transmitter Subsystem provides a set of API functions for application code to use. On top of that, when HDMI 1.4/2.0 Transmitter Subsystem hardwa…

79, HDMI 1.4/2.0 TX Subsystem 79 PG235 October 4, 2017 www.xilinx.com Appendix A: Verification, Compliance, and Interoperability Table A-1, Table A-2, and Table A-3 show the video resolutions that were tested as part of the release for different video formats. The following limitations apply: • …

4, HDMI 1.4/2.0 TX Subsystem 4 PG235 October 4, 2017 www.xilinx.com Product Specification Introduction The HDMI 1.4/2.0 Transmitter Subsystem is a hierarchical IP that bundles a collection of HDMI® TX IP sub-cores and outputs them as a single IP. It is an out-of-the-box ready-to-use HDMI 1.4/2.…

85, HDMI 1.4/2.0 TX Subsystem 85 PG235 October 4, 2017 www.xilinx.com Appendix B: Debugging Interface Debug AXI4-Lite Interfaces Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is v…