Xilinx I2S Product Manual

Product Manual for Xilinx I2S Receiver (40 pages)

Specifications:

844/844800-i2s.pdf file (13 Oct 2023)
  • Manufacturer: Xilinx
  • Category of Device: Receiver
  • Document: I2S, File Type: PDF Product Manual
  • Updated: 13-10-2023
  • Count of Pages: 40
Download I2S Manual (40 pages)

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Data: UPD 13th October 2023

Xilinx I2S Receiver PDF Product Manual (Updated: Friday 13th of October 2023 04:31:25 AM)

Rating: 4.1 (rated by 75 users)

Compatible devices: Vivado MIPI CSI-2, KRC-509S, X-HM32VD-K, SAT-A4 - Digital Satellite System, Varium C1100, T24-ANTA, LogiCORE IP, USER GUIDE.

Recommended Documentation:

Text Version of Xilinx I2S Receiver Manual (Summary of Contents)

(Ocr-Read of Xilinx I2S Document (Main Content), UPD: 13 October 2023)
  • 19, Xilinx I2S Table 19: Receiver Interrupt Status (0×14) Bit Default Value Access Type Description 31:2 Reserved 1 0 R/W1C Overflow Interrupt: This bit is set when the IP is not able to send all enabled audio channels in time. This interrupt would indicate loss of samples. Write a ‘1’ to …

  • 18, Table 16: Receiver Core Configuration (0x04) (cont'd) Bit Default Value Access Type Description 7:1 RSVD 0 RO Is I2S Master: Indicates if the core has been generated as an I2S Master or Slave. 1 = I2S Master Control Register (0x08) This register provides capability to enable/disable the…

  • 8, Chapter 3 Product Specification The I2S Tramsmier and I2S Receiver IPs can be used to develop audio soluon using I2S ADC/ DACs. These IPs support any sampling rate and are very easy to congure with minimal register programming. Figure 1: TX Audio Sampling AES3 Audio Decode…

  • 12, Table 2: Register Address Space (cont'd) Address (hex) Register Name 0x50 AES Channel Status 0: Register that returns the LSB 32 bit of the AES Channel Status 0x54 AES Channel Status 1: Register that returns the next LSB 32 bit of the AES Channel Status 0x58 AES Channel Status 2: Register tha…

  • 20, Channel 2/3 Control (0x34) The IP provides a mechanism to route the audio from any I2S input. For example, audio received on I2S Channel 0 can be routed to any of the 8 audio channels. Similarly audio received on one I2S channel can be routed to all of the 8 audio channels. Table 22: Receiver Ch…

  • 29, Figure 6: I2S Transmitter Configuration Tab Field Descriptions • Component Name : The base name of the output les generated for the core. Names must begin with a leer and can be composed of any of the following characters: a- z, 0 to 9, and "_". • Audio Channels : …

DOC-9f183b62:

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