Xilinx KC705 Operation & User’s Manual

52, KC705 Evaluation Board 52 UG810 (v1.8) March 20, 2018 www.xilinx.com Chapter 1: KC705 Evaluation Board Features Table 1-23 lists the connections between the FPGA and the LCD header. For more information about the Displaytech S162D LCD, see [Ref 18]. I2C Bus Switch [Figure 1-2, callout 20] Th…

85, Xilinx KC705 KC705 Evaluation Board 85 UG810 (v1.8) March 20, 2018 www.xilinx.com Appendix A: Default Switch and Jumper Settings 5 J56 None U56 UCD9248 RESET_B = LOGIC 1 (NOT RESET) 40 6 J65 1-2 FMC VADJ = ON 36 7 J68 1-2 XADC_VCC5V0 =VCC5V0 (5V) 31 3-pin 8 J27 2-3 SFP RX BW = FULL 22 9 J28 2-3 SFP TX BW = F…

45, KC705 Evaluation Board 45 UG810 (v1.8) March 20, 2018 www.xilinx.com Chapter 1: KC705 Evaluation Board Features Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet MAC User Guide (PG051) [Ref 14]. For more information about the Marvell 88E1111, s…

28, KC705 Evaluation Board 28 UG810 (v1.8) March 20, 2018 www.xilinx.com Chapter 1: KC705 Evaluation Board Features Clock Generation There are five clock sources available for the FPGA fabric on the KC705 board (refer to Table 1-8). Table 1-9 lists the pin-to-pin connections from each clock source to …

106, KC705 Evaluation Board 106 UG810 (v1.8) March 20, 2018 www.xilinx.com Appendix C: Master Constraints File Listing set_property PACKAGE_PIN U25 [get_ports PHY_RXD1] set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD1] set_property PACKAGE_PIN T25 [get_ports PHY_RXD2] set_property IOSTANDARD L…