Analog Devices ADSP-21020 Manual, Specification Sheet

23, ADSP-21020 REV. C –23– TCK TMS,TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS t STAP t HTAP t DTDO t SSYS t HSYS t DSYS t TCK Figure 12. IEEE 1149.1 Test Access Port …

9, ADSP-21020 REV. C –9– Table III. Universal Registers Name Function Register File R15–R0 Register file locations Program Sequencer PC* Program counter; address of instruction cur- rently executing PCSTK Top of PC stack PCSTKP PC stack pointer FADDR* Fetch address DADDR* Decode addr…

11, Analog Devices ADSP-21020 ADSP-21020 REV. C –11– Table Vll. Multifunction Compute Operations Fixed-Point Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12 Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-…

18, ADSP-21020 REV. C –18– Memory Read K/B/T Grade K/B/T Grade B/T Grade K Grade 20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependence* Parameter Min Max Min Max Min Max Min Max Min Max Unit Timing Requirement: t DAD Address, Select to Data Valid 37 27 20 17 37 + DT ns t DRLD xRD Low to Data Vali…

29, ADSP-21020 REV. C –29– DMD7 DMD8 DMA14 DMA13 DMD12 DMD14 DMD18 DMD21 DMD22 DMD26 DMD32 DMD33 DMD37 DMD39 DMA21 DMA17 DMA16 EVDD DMD23 DMD29 DMD34 DMA22 BG BR BOTTOM VIEW (PINS UP) PMD31 PMD35 PMD39 PMD40 PMD44 PMWR PMACK RCOMP PMD27 PMD30 PMD32 PMD37 NC PMD42 PMTS NC NC CLKIN DMACK DMWR PMD11…

26, ADSP-21020 REV. C –26– ENVIRONMENTAL CONDITIONS The ADSP-21020 is available in a Ceramic Pin Grid Array (CPGA). The package uses a cavity-down configuration which gives it favorable thermal characteristics. The top surface of the package contains a raised copper slug from which much of the …