Cypress Semiconductor CY7C1339G Manual, Specification Sheet

14, CY7C1339G Document #: 38-05520 Rev. *F Page 14 of 18 ZZ Mode Timing [22, 23] Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 23. DQs are in high-Z when exiting ZZ sleep mode. Switching Wa…

8, Cypress Semiconductor CY7C1339G CY7C1339G Document #: 38-05520 Rev. *F Page 8 of 18 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied..............................…

17, CY7C1339G Document #: 38-05520 Rev. *F Page 17 of 18 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypr…

13, CY7C1339G Document #: 38-05520 Rev. *F Page 13 of 18 Read/Write Cycle Timing [18, 20, 21] Notes: 20. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 21. GW is HIGH. Switching Waveforms (continued) t CYC t CL CLK ADSP t ADH t …

18, CY7C1339G Document #: 38-05520 Rev. *F Page 18 of 18 Document History Page Document Title: CY7C1339G 4-Mbit (128K x 32) Pipelined Sync SRAM Document Number: 38-05520 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 224368 See ECN RKF New data sheet *A 288909 See ECN VBL In Order…

11, CY7C1339G Document #: 38-05520 Rev. *F Page 11 of 18 Switching Waveforms Read Cycle Timing [18] Note: 18. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK ADSP t ADH t ADS ADD…