Cypress Semiconductor CY7C1516KV18 Manual, Specification Sheet

19, CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev. *E Page 19 of 30 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either…

28, CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev. *E Page 28 of 30 167 CY7C1516KV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1527KV18-167BZC CY7C1518KV18-167BZC CY7C1520KV18-167BZC CY7C1516KV18-167BZXC…

24, CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev. *E Page 24 of 30 Output Times t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold after Output C/C Cloc…

21, CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev. *E Page 21 of 30 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 370 mA (x9) 370 (x18) 380 (x36) 450 167 MHz (x8) 340 mA (x9) 340 (x18) 340 (x36) 400 I SB1…

8, Cypress Semiconductor CY7C1516KV18 CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev. *E Page 8 of 30 Functional Overview The CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency…

23, CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18 Document Number: 001-00437 Rev. *E Page 23 of 30 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consortium Parameter Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max Min Max Min…