Cypress Semiconductor MoBL-USB CY7C68053 Manual, Specification Sheet

19, Cypress Semiconductor MoBL-USB CY7C68053 CY7C68053 Document # 001-06120 Rev *F Page 19 of 39 E6A1 1 EP1OUTCS Endpoint 1 OUT Control and Status 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb E6A2 1 EP1INCS Endpoint 1 IN Control and Status 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb E6A3 1 EP2CS Endpoint 2 Control and Status 0 NPAK2…

3, CY7C68053 Document # 001-06120 Rev *F Page 3 of 39 3.3 I 2 C™ Bus FX2LP18 supports the I 2 C bus as a master only at 100-/400- KHz. SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to either V CC or V CC_IO , even if no I 2 C device is connec…

15, CY7C68053 Document # 001-06120 Rev *F Page 15 of 39 2G IFCLK I/O/Z Z Interface Clock, used for synchronously clocking data into or out of the slave FIFO’s. IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1) the …

39, CY7C68053 Document # 001-06120 Rev *F Page 39 of 39 Document History Page Document Title: CY7C68053 MoBL-USB FX2LP18 USB Microcontroller Document Number: 001-06120 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 430449 03/03/06 OSG New data sheet *A 434754 03/24/06 O…

28, CY7C68053 Document # 001-06120 Rev *F Page 28 of 39 9.5 Slave FIFO Synchronous Write Z Z t SFD t FDH DATA IFCLK SLWR FLAGS t WRH t XFLG t IFCLK t SWR N Figure 9-4. Slave FIFO Synchronous Write Timing Diagram [17] Table 9-6. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCL…

33, CY7C68053 Document # 001-06120 Rev *F Page 33 of 39 9.13 Sequence Diagram Various sequence diagrams and examples are presented in this section. 9.13.1 Single and Burst Synchronous Read Example Figure 9-13 shows the timing relationship of the SLAVE FIFO signals during a synchronou…